ELECTRICAL CIRCUIT FOR VOLTAGE CONVERSION

• US 20170288533A1
• Filed: 06/16/2017
• Published: 10/05/2017
• Est. Priority Date: 10/28/2014
• Status: Abandoned Application

• Current Assignee: Smart Prong Technologies, Inc.
• Original Assignee: Advanced Charging Technologies LLC
• Inventors: Sandusky, Randall L., Farooqi, Neaz E.
• Application Number:
  US15/625,939
• Publication Number:
  US 20170288533A1
• Time in Patent Office: Days
• CPC Class Codes: G05F 1/462 as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
• CPC Class Codes: H02M 1/007 Plural converter units in cascade push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826
• CPC Class Codes: H02M 3/072 adapted to generate an output voltage whose value is lower than the input voltage
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H03M 7/10 the radix thereof being negative

Abstract

A circuit includes a second voltage converter electrically coupled to a comparator and first voltage converter. The first voltage converter receives first and second clocks and an input signal at a first voltage and generates an intermediate signal at a second voltage based on the input signal and the first and second clocks. The second voltage converter receives the intermediate signal, the second clock, and a comparison signal and generates an output signal at a third voltage based on the intermediate and comparison signals and the second clock. The comparator receives a reference voltage, the output signal, and the first clock, compares the reference voltage and output signal, and generates the comparison signal based on the first clock and the comparison of the reference voltage and output signal. The second voltage converter adjusts the third voltage of the output signal to approach the reference voltage based on the comparison signal.

Claims

1. A voltage conversion circuit comprising:

a first stage voltage converter configured to;

receive an input signal at a first voltage level;

receive a first clock signal and a second clock signal; and

generate an intermediate signal at a second voltage level based on the input signal, the first clock signal, and the second clock signal;

a second stage voltage converter electrically coupled in series with the first stage voltage converter and configured to;

receive the intermediate signal;

receive the second clock signal and a combined comparison signal; and

generate an output signal at a third voltage level based on the intermediate signal, the combined comparison signal, and the second clock signal;

a comparison circuit electrically coupled in parallel to the second stage voltage converter and configured to;

receive a reference signal at a fourth voltage level;

receive the output signal and the first clock signal;

compare the reference signal and the output signal; and

generate the combined comparison signal based on the first clock signal and the comparison of the reference signal and the output signal, wherein the second stage voltage converter is configured to adjust the third voltage level of the output signal to approach the fourth voltage level of the reference signal based on the combined comparison signal.

2. The voltage conversion circuit of claim 1, wherein the comparison circuit comprises:

a comparator configured to;

receive the reference signal and the output signal;

compare the reference signal and the output signal; and

generate a comparison signal based on the comparison of the reference signal and the output signal; and

a logic circuit configured to;

receive the first clock signal and the comparison signal; and

generate the combined comparison signal based on the first clock signal and the comparison signal.

3. The voltage conversion circuit of claim 1, wherein the comparison circuit is electrically coupled to the first stage voltage converter, wherein the first stage voltage converter is configured to:

receive the combined comparison signal; and

generate the intermediate signal based on the input signal, the combined comparison signal, and the second clock signal.

4. The voltage conversion circuit of claim 1, wherein the comparison circuit includes a first comparison circuit, the reference signal includes a first reference signal, the combined comparison signal includes a first combined comparison signal, and the first stage voltage converter is configured to receive a second combined comparison signal, the voltage conversion circuit comprising:

a second comparison circuit electrically coupled in parallel to the first stage voltage converter and configured to;

receive a second reference signal at a fifth voltage level;

receive the intermediate signal and the first clock signal;

compare the second reference signal and the intermediate signal; and

generate the second combined comparison signal based on the first clock signal and the comparison of the second reference signal and the intermediate signal, wherein the first stage voltage converter is configured to adjust the second voltage level of the intermediate signal to approach the fifth voltage level of the second reference signal based on the second combined comparison signal.

5. The voltage conversion circuit of claim 1, wherein the comparison circuit is configured to stop generating the combined comparison signal in response to the third voltage level of the output signal being the same or similar to the fourth voltage level of the reference signal.

6. The voltage conversion circuit of claim 1, wherein the second clock signal includes an electrical signal generated by a Dickson charge pump.

7. The voltage conversion circuit of claim 1, wherein the first stage voltage converter comprises a first capacitive element and a second capacitive element.

8. The voltage conversion circuit of claim 7, wherein the voltage conversion circuit comprises a third capacitive element electrically coupled to the first stage voltage converter and the second stage voltage converter and ground.

9. A voltage conversion circuit comprising:

a multiple stage voltage converter configured to;

receive an input signal at a first voltage level;

receive a first clock signal and a second clock signal; and

generate an intermediate signal at a second voltage level based on the input signal, the first clock signal, and the second clock signal;

a switching inductive circuit electrically coupled in series with the multiple stage voltage converter and configured to;

receive the intermediate signal;

receive a comparison signal; and

generate an output signal at a third voltage level based on the intermediate signal and the comparison signal; and

a regulator circuit electrically coupled in parallel to the switching inductive circuit and configured to;

receive the output signal;

receive a reference signal at a fourth voltage level;

receive a third clock signal;

compare the output signal and the reference signal; and

generate the comparison signal based on the third clock signal and the comparison of the output signal and the reference signal, wherein the switching inductive circuit is configured to adjust the third voltage level of the output signal to approach the fourth voltage level of the reference signal based on the comparison signal.

10. The voltage conversion circuit of claim 9, wherein the switching inductive circuit comprises a FET transistor, an inductor, a capacitor, and a diode.

11. The voltage conversion circuit of claim 9, wherein the switching inductive circuit comprises:

a switching element configured to;

receive the intermediate signal and the comparison signal; and

generate an internal signal based on the comparison signal and the intermediate signal; and

an inductive circuit configured to;

receive the internal signal; and

generate the output signal by modifying the internal signal.

12. The voltage conversion circuit of claim 9, wherein the second clock signal includes an electrical signal generated by a Dickson charge pump.

13. The voltage conversion circuit of claim 9, wherein the third clock signal includes a pulse width modulated signal.

14. The voltage conversion circuit of claim 9, wherein the multiple stage voltage converter comprises:

a first stage voltage converter;

a second stage voltage converter electrically coupled in series with the first stage voltage converter;

a first capacitive element electrically coupled in series with the first stage voltage converter;

a second capacitive element electrically coupled to the first stage voltage converter;

a third capacitive element electrically coupled to the second stage voltage converter; and

a fourth capacitive element electrically coupled to the second stage voltage converter.

15. The voltage conversion circuit of claim 14, wherein the voltage conversion circuit comprises a fifth capacitive element electrically coupled to the first stage voltage converter, the second stage voltage converter and ground.

16. A voltage conversion circuit comprising:

a multiple stage voltage converter configured to;

receive a boost signal at a first voltage level;

receive a first clock signal and a second clock signal; and

generate an output signal at a second voltage level based on the boost signal, the first clock signal, and the second clock signal; and

a boost switching regulator electrically coupled in series with the multiple stage voltage converter and configured to;

receive an input signal, a third clock signal, and the output signal;

receive a reference signal at a third voltage level;

compare the reference signal and the output signal; and

generate the boost signal based on the input signal, the third clock signal, and the comparison of the reference signal and the output signal, wherein the boost switching regulator is configured to adjust the first voltage level of the boost signal to cause the second voltage level of the output signal generated by the multiple stage voltage converter to approach the third voltage level of the reference signal.

17. The voltage conversion circuit of claim 16, wherein the second clock signal includes an electrical signal generated by a Dickson charge pump.

18. The voltage conversion circuit of claim 16, wherein the third clock signal includes a pulse width modulated signal.

19. The voltage conversion circuit of claim 16, wherein the boost switching regulator comprises an inductive circuit that is driven by the third clock signal and is configured to regulate the first voltage level of the boost signal.

20. The voltage conversion circuit of claim 16, wherein the multiple stage voltage converter comprises:

a first stage voltage converter;

a second stage voltage converter electrically coupled in series with the first stage voltage converter;

a first capacitive element electrically coupled to the first stage voltage converter;

a second capacitive element electrically coupled to the first stage voltage converter;

a third capacitive element electrically coupled to the second stage voltage converter;

a fourth capacitive element electrically coupled to the second stage voltage converter; and

a fifth capacitive element electrically coupled to the first stage voltage converter, the second stage voltage converter, and ground.