MULTI-MODE STACKED AMPLIFIER

• US 20170288609A1
• Filed: 03/30/2017
• Published: 10/05/2017
• Est. Priority Date: 04/01/2016
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Soliman, Yasser Khairat
• Granted Patent: US 10,110,168 B2
• Time in Patent Office: Days
• CPC Class Codes: H03F 1/0216 Continuous control
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0266 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/312 the loading circuit of an amplifying stage comprising one or more switches
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/213 in integrated circuits
• CPC Class Codes: H03F 3/245 with semiconductor devices only

Abstract

Aspects of this disclosure relate to an amplification circuit that includes a stacked amplifier and a bias circuit. The stacked amplifier includes at least a first transistor and a second transistor in series with each other. The stacked amplifier is operable in at least a first mode and a second mode. The bias circuit is configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode. In certain embodiments, the amplification circuit can be a power amplifier stage configured to receive a supply voltage that has a different voltage level in the first mode than in the second mode.

Claims

1. An amplification circuit comprising:

a stacked amplifier including at least a first transistor and a second transistor in series with each other, the stacked amplifier operable in at least a first mode and a second mode; and

a bias circuit configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode.

2. The amplification circuit of claim 1 wherein the stacked amplifier includes a third transistor in series with the first transistor and the second transistor.

3. The amplification circuit of claim 1 wherein the stacked amplifier is configured to amplify a radio frequency signal.

4. The amplification circuit of claim 1 wherein the bias circuit is configured to bias the second transistor in a saturation region of operation in the second mode.

5. The amplification circuit of claim 1 further comprising a first stage amplifier having an output electrically connected to an input of the stacked amplifier by way of a matching network.

6. The amplification circuit of claim 1 wherein the first transistor and the second transistor are semiconductor-on-insulator transistors.

7. The amplification circuit of claim 1 wherein the stacked amplifier is operable in a third mode, the bias circuit is configured to bias the second transistor to the linear region of operation in the third mode, and the stacked amplifier is configured to receive a supply voltage that has a different voltage level in the first mode than in the third mode.

8. The amplification circuit of claim 1 wherein the second mode is associated with a lower power than the first mode.

9. The amplification circuit of claim 1 wherein the stacked amplifier is configured to receive a supply voltage, the supply voltage having a lower voltage level in the second mode than in the first mode.

10. The amplification circuit of claim 1 further comprising an output matching network electrically connected to an output of the stacked amplifier, and the output matching network being either a class F output matching network or a class AB output matching network.

11. A power amplifier system comprising:

a power amplifier stage including at least a first transistor and a second transistor in series with each other, the power amplifier stage operable in at least a first mode and a second mode;

a bias circuit configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode; and

a supply control circuit configured to provide a supply voltage to the power amplifier stage such that the supply voltage has a higher voltage level in the first mode than in the second mode.

12. The power amplifier system of claim 11 wherein the supply control circuit is configured to receive a mode control signal and to adjust the voltage level of the supply voltage based on the mode control signal.

13. The power amplifier system of claim 11 wherein the supply control circuit is configured to provide the supply voltage such that the supply voltage has a different voltage level in a third mode than in both the first mode and the second mode.

14. The power amplifier system of claim 11 wherein the power amplifier stage includes a third transistor in series with the first transistor and the second transistor.

15. The power amplifier system of claim 11 wherein the bias circuit is configured to receive a mode control signal and to bias the second transistor based on the mode control signal.

16. A front end system comprising:

a low noise amplifier;

a power amplifier circuit including a stacked amplifier including at least a first transistor and a second transistor in series with each other, the stacked amplifier operable in at least a first mode and a second mode, the power amplifier circuit further including a bias circuit configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode; and

a switch electrically connected to the low noise amplifier and the power amplifier circuit.

17. The front end system of claim 16 wherein the switch is multi-throw switch having at least a first throw electrically coupled to the power amplifier circuit and a second throw electrically coupled to the low noise amplifier.

18. The front end system of claim 17 further comprising a bypass path electrically coupled to a third throw of the multi-throw switch.

19. The front end system of claim 16 wherein the low noise amplifier and the power amplifier circuit are embodied on a single die.

20. The front end system of claim 16 further comprising a package enclosing the power amplifier circuit, the low noise amplifier, and the switch.