SURFACE-MOUNTABLE POWER DELIVERY BUS BOARD

• US 20170290158A1
• Filed: 03/30/2016
• Published: 10/05/2017
• Est. Priority Date: 03/30/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Pihlman, Jeffrey A., Tomlin, John C.
• Granted Patent: US 10,123,419 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01R 12/727 Coupling devices presenting arrays of contacts
• CPC Class Codes: H05K 1/0262 Arrangements for regulating voltages or for using plural voltages
• CPC Class Codes: H05K 1/0296 Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295 H05K1/11 takes precedence; lay-out adapted to mounted component configuration H05K1/18
• CPC Class Codes: H05K 1/111 Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 1/14 Structural association of two or more printed circuits providing electric connection to or between printed circuits H05K1/11, H01R12/00
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/144 Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/041 Stacked PCBs, i.e. having neither an empty space nor mounted components in between
• CPC Class Codes: H05K 2201/042 Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
• CPC Class Codes: H05K 2201/045 Hierarchy auxiliary PCB, i.e. more than two levels of hierarchy for daughter PCBs are important
• CPC Class Codes: H05K 2201/10037 Printed or non-printed battery
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 2201/2036 Permanent spacer or stand-off in a printed circuit or printed circuit assembly
• CPC Class Codes: H05K 3/10 in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
• CPC Class Codes: H05K 3/341 Surface mounted components
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457

Abstract

IC device assemblies including a power delivery bus board that is mounted to a primary PCB (i.e., motherboard) that further hosts a power-sink device and a power-source device. The bus board, as a secondary PCB, may be surface-mounted on a back side of the primary PCB opposite the power source and sink devices, which are mounted on the front side of the primary PCB. The bus board need only be dimensioned so as to bridge a length between first and second back-side regions of the primary PCB that are further coupled to a portion of the front-side pads employed by the power-sink device. The secondary PCB may be purpose-built for conveying power between the source and sink devices, and include, for example, short, wide traces, that may be formed from multiple heavyweight metallization layers.

Claims

1. An integrated circuit (IC) device assembly, comprising:

a primary printed circuit board (PCB) further including;

first front-side pads disposed within a first front-side region of the primary PCB;

second front-side pads disposed within a second front-side region of the primary PCB;

first back-side pads disposed within a first back-side region, opposite the first front-side region, wherein the first back-side pads are electrically coupled through the primary PCB to the first front-side pads; and

second back-side pads disposed within a second back-side region, opposite the second front-side region, wherein the second back-side pads are electrically coupled through the primary PCB to a first portion of the second front-side pads; and

a secondary PCB mounted to a back side of the primary PCB, the secondary PCB bridging a length between the first and second back-side regions and comprising two or more layers of conductive traces electrically coupling the first and second back-side pads.

2. The assembly of claim 1, further comprising:

a power-source device mounted to the first front-side pads; and

a power-sink device mounted to the second front-side pads.

3. The assembly of claim 2, wherein the power-sink device is in a ball-grid array (BGA) package and the second front-side pads are arrayed in a first pattern to accommodate the BGA package.

4. The assembly of claim 3, wherein the power-sink device comprises a number of power and ground connections equal to the first portion of the second front-side pads.

5. The assembly of claim 2, wherein:

the power-source device comprises one or more voltage regulators; and

the power-sink device comprises a microprocessor.

6. The assembly of claim 5, wherein:

the voltage regulators include a plurality of power rails; and

the two or more layers of conductive traces in the secondary PCB include at least a first conductive trace coupled to a first of the power rails, and at least a second conductive trace coupled to a second of the power rails.

7. The assembly of claim 6, wherein at least two of the two or more layers of conductive traces are coupled to a first of the power rails.

8. The assembly of claim 1, wherein the secondary PCB further comprises:

a first plurality of conductive surface features soldered to the first back-side pads, the first plurality of conductive surface features coupled to the conductive traces through one or more first vias extending through the secondary PCB; and

a second plurality of conductive surface features soldered to the second back-side pads, the second plurality of conductive surface features coupled to the conductive traces through one or more second vias extending through the secondary PCB.

9. The assembly of claim 8, wherein the first and second plurality of conductive surface features comprise BGA pads coupled by solder balls to the first and second back-side pads.

10. The assembly of claim 9, wherein:

the first portion of the second front-side pads form an array having a first pattern to accommodate a ball grid array (BGA) package of a power-sink device; and

the second plurality of BGA pads on the secondary PCB are in an array matching the first pattern to accommodate solder balls interconnecting the second plurality of BGA pads to the second back-side pads.

11. The assembly of claim 1, wherein:

a second portion of the second front-side pads form a perimeter surrounding the first portion of the second front-side pads;

the primary PCB comprises two or more conductive trace layers comprising signal traces escaping from the second portion of the second front-side pads; and

the signal traces extend into a region of the primary PCB that is bridged by the secondary PCB.

12. The assembly of claim 9, wherein the secondary PCB further comprises one or more discrete components disposed in on a surface region of the secondary PCB between the first and second plurality of conductive surface features.

13. The assembly of claim 12, wherein:

the two or more conductive traces include one or more ground traces and one or more power traces; and

the discrete components are decoupling capacitors coupled across the ground and power traces.

14. A computer platform, comprising:

a primary printed circuit board (PCB) further including;

first front-side pads disposed within a first front-side region of the primary PCB;

second front-side pads disposed within a second front-side region of the primary PCB;

first back-side pads disposed within a first back-side region, opposite the first front-side region, wherein the first back-side pads are electrically coupled through the primary PCB to the first front-side pads; and

second back-side pads disposed within a second back-side region, opposite the second front-side region, wherein the second back-side pads are electrically coupled through the primary PCB to a first portion of the second front-side pads;

one or more voltage regulators mounted to the first front-side pads;

one or more microprocessors mounted to the second front-side pads, the microprocessors having a number of power and ground connections equal to the first portion of the second front-side pads; and

a secondary PCB mounted to a back side of the primary PCB, the secondary PCB bridging a length between the first and second back-side regions and comprising two or more layers of conductive traces electrically coupling the first and second back-side pads.

15. The platform of claim 14, wherein:

the microprocessors are in a ball-grid array (BGA) package and the first front-side pads arrayed in a first pattern to accommodate the BGA package;

the secondary PCB further comprises;

a first plurality of BGA pads soldered to the first back-side pads, the first plurality of BGA pads coupled to the conductive traces through one or more first vias extending through the secondary PCB;

a second plurality of BGA pads soldered to the second back-side pads, the second plurality of BGA pads coupled to the conductive traces through one or more second vias extending through the secondary PCB; and

the second plurality of BGA pads on the secondary PCB are in an array matching the first pattern to accommodate solder balls interconnecting the second plurality of BGA pads to the second back-side pads.

16. The platform of claim 14, further comprising a battery coupled to an input-side of the voltage regulators.

17. A method of assembling an printed circuit assembly (PCA), the method comprising:

receiving a primary printed circuit board (PCB) including;

first front-side pads disposed within a first front-side region of the primary PCB;

second front-side pads disposed within a second front-side region of the primary PCB; and

first back-side pads disposed within a first back-side region, opposite the first front-side region, wherein the first back-side pads are electrically coupled through the primary PCB to the first front-side pads; and

second back-side pads disposed within a second back-side region, opposite the second front-side region, wherein the second back-side pads are electrically coupled through the primary PCB to a first portion of the second front-side pads;

mounting a power-source device to the first front-side pads;

mounting a power-sink device to the second front-side pads; and

mounting a secondary PCB to a back side of the primary PCB, the secondary PCB bridging a length between the first and second back-side regions and comprising two or more layers of conductive traces electrically coupling the first and second back-side pads.

18. The method of claim 17, wherein:

the power-source device comprises one or more voltage regulators providing a plurality of power rails;

the power-sink device comprises a microprocessor;

the two or more layers of conductive traces in the secondary PCB include at least a first conductive trace coupled to a first of the power rails, and at least a second conductive trace coupled to a second of the power rails.

19. The method of claim 17, wherein mounting the secondary PCB includes:

soldering a first plurality of conductive surface features to the first back-side pads, the first plurality of conductive surface features coupled to the conductive traces through one or more first vias extending through the secondary PCB; and

soldering a second plurality of conductive surface features to the second back-side pads, the second plurality of conductive surface features coupled to the conductive traces through one or more second vias extending through the secondary PCB.

20. The method of claim 17, further comprising:

soldering one or more discrete components onto a surface region of the secondary PCB between the first and second plurality of conductive surface features.