SCALABLE DATA ACCESS SYSTEM AND METHODS OF ELIMINATING CONTROLLER BOTTLENECKS
First Claim
1. A computing system of the type comprising at least one processor (CPU) coupled through at least one front-end storage controller (nFE_SAN) to a storage-area network (SAN), the SAN coupled through at least one back-end storage controller (nBE_SAN) to a plurality of storage devices, the improvement comprising:
- a first nFE_SAN of the at least one nFE_SAN having a first and a second write-back cache module configured to, upon receiving a write command addressed to a data block, to receive write data from the at least one CPU, maintain a first copy of the write data in the first write-back cache module and a second copy of the write data in the second write-back cache module of data written by the at least one processor to the storage devices until the data is written to the at least one nBE_SAN, the first write-back cache module configured to receive power from a first power supply and the second write-back cache module configured to receive power from a second power supply;
the first nFE_SAN coupled to the at least one nBE_SAN through a first SAN and through a second SAN;
the nFE_SAN configured to be capable of transmitting data from the first write-back cache module to the at least one nBE_SAN over the first SAN when the first power supply is operational, and capable of transmitting data from the second write-back cache module to the at least one nBE_SAN when the second power supply is operational and the first power supply not operational; and
the nFE_SAN configured to provide a write command complete response to the at least one CPU upon receiving the write data into the first and second writeback cache.
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Accused Products
Abstract
A data access system has host computers having front-end controllers nFE_SAN connected via a bus or network interconnect to back-end storage controllers nBE_SAN, and physical disk drives connected via network interconnect to the nBE_SANs to provide a distributed, high performance, policy based or dynamically reconfigurable, centrally managed, data storage acceleration system. The hardware and software architectural solutions eliminate BE_SAN controller bottlenecks and improve performance and scalability. In an embodiment, the nBE_SAN (BE_SAN) firmware recognize controller overload conditions, informs Distributed Resource Manager (DRM), and, based on the DRM provided optimal topology information, delegates part of its workload to additional controllers. The nFE_SAN firmware and additional hardware using functionally independent and redundant CPUs and memory that mitigate single points of failure and accelerates write performance. The nFE_SAN and FE_SAN controllers facilitate Converged I/O Interface by simultaneously supporting storage I/O and network traffic.
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Citations
13 Claims
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1. A computing system of the type comprising at least one processor (CPU) coupled through at least one front-end storage controller (nFE_SAN) to a storage-area network (SAN), the SAN coupled through at least one back-end storage controller (nBE_SAN) to a plurality of storage devices, the improvement comprising:
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a first nFE_SAN of the at least one nFE_SAN having a first and a second write-back cache module configured to, upon receiving a write command addressed to a data block, to receive write data from the at least one CPU, maintain a first copy of the write data in the first write-back cache module and a second copy of the write data in the second write-back cache module of data written by the at least one processor to the storage devices until the data is written to the at least one nBE_SAN, the first write-back cache module configured to receive power from a first power supply and the second write-back cache module configured to receive power from a second power supply; the first nFE_SAN coupled to the at least one nBE_SAN through a first SAN and through a second SAN; the nFE_SAN configured to be capable of transmitting data from the first write-back cache module to the at least one nBE_SAN over the first SAN when the first power supply is operational, and capable of transmitting data from the second write-back cache module to the at least one nBE_SAN when the second power supply is operational and the first power supply not operational; and the nFE_SAN configured to provide a write command complete response to the at least one CPU upon receiving the write data into the first and second writeback cache. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of writing write data to at least one storage device comprising:
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generating a write request in a computer processor; passing the write request to a front-end storage controller (nFE_SAN); copying the write data to a first and a second cache memory of the nFE_SAN; generating a write lock request and transmitting the write lock request from the nFE_SAN over a network interconnect selected from a first and a second storage area interconnect to a back-end storage controller (nBE_SAN); returning a write lock grant from the nBE_SAN to the nFE_SAN; upon completing copying the write data to the first and second cache memory of the nFE_SAN and receiving the write lock grant from the nBE_SAN, the nFE_SAN providing a write complete signal to the computer processor; copying the write data over a network interconnect selected from the first and second storage area interconnect to the nBE_SAN; and writing, by the BE_SAN, the write data to the at least one storage device. - View Dependent Claims (12, 13)
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Specification