METHODS FOR SiO2 FILLING OF FINE RECESSED FEATURES AND SELECTIVE SiO2 DEPOSITION ON CATALYTIC SURFACES

• US 20170294339A1
• Filed: 04/11/2017
• Published: 10/12/2017
• Est. Priority Date: 04/12/2016
• Status: Active Grant

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Tapily, Kandabara N.
• Granted Patent: US 10,049,913 B2
• Time in Patent Office: Days
• CPC Class Codes: C23C 16/402 Silicon dioxide
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02277 the reactions being activated by other means than plasma or thermal, e.g. photo-CVD
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Abstract

Methods for void-free SiO₂ filling of fine recessed features and selective SiO₂ deposition on catalytic surfaces are described. According to one embodiment, the method includes providing a substrate containing recessed features, coating surfaces of the recessed features with a metal-containing catalyst layer, in the absence of any oxidizing and hydrolyzing agent, exposing the substrate at a substrate temperature of approximately 150° C. or less, to a process gas containing a silanol gas to deposit a conformal SiO₂ film in the recessed features, and repeating the coating and exposing at least once to increase the thickness of the conformal SiO₂ film until the recessed features are filled with SiO₂ material that is void-free and seamless in the recessed features. In one example, the recessed features filled with SiO₂ material form shallow trench isolation (STI) structures in a semiconductor device.

Claims

1. A substrate processing method, the method comprising:

providing a substrate containing recessed features;

coating surfaces of the recessed features with a metal-containing catalyst layer;

in the absence of any oxidizing and hydrolyzing agent, exposing the substrate at a substrate temperature of approximately 150°

C. or less, to a process gas containing a silanol gas to deposit a conformal SiO₂ film in the recessed features; and

repeating the coating and exposing at least once to increase the thickness of the conformal SiO₂ film until the recessed features are filled with SiO₂ material that is void-free and seamless in the recessed features.

2. The method of claim 1, wherein the silanol gas is selected from the group consisting of tris(tert-pentoxy) silanol, tris(tert-butoxy) silanol, and bis(tert-butoxy)(isopropoxy) silanol.

3. The method of claim 1, wherein the metal-containing catalyst layer contains aluminum, titanium, or a combination thereof.

4. The method of claim 3, wherein the metal-containing catalyst layer is selected from the group consisting of Al, Al₂O₃, AlN, AlON, an Al-containing precursor, Al-alloys, CuAl, TiAlN, TaAlN, Ti, TiAlC, TiO₂, TiON, TiN, a Ti-containing precursor, Ti-alloys, and combinations thereof.

5. The method of claim 1, wherein the coating includes exposing the substrate to AlMe₃ gas.

6. The method of claim 1, wherein the coating and exposing are performed a plurality of times, the first time the sidewalls of the recessed features are coated with Al₂O₃, and thereafter the sidewalls are coated with AlMe₃ each time the coating is repeated.

7. The method of claim 1, wherein coating and exposing are performed a plurality of times, the first time the sidewalls are coated with HfO₂, and Al₂O₃ on the HfO₂, and thereafter the sidewalls are coated with AlMe₃ each time the coating is repeated.

8. The method of claim 1, wherein the substrate temperature is approximately 100°

C. or less, during the exposing.

9. The method of claim 1, wherein the process gas consists of a silanol gas and an inert gas.

10. The method of claim 1, wherein the recessed features filled with SiO₂ material form shallow trench isolation (STI) structures in a semiconductor device.

11. The method of claim 1, further comprising

removing excess SiO₂ from above the recessed feature in a planarizing process.

12. The method of claim 11, wherein the removing is performed using chemical-mechanical planarization (CMP).

13. A substrate processing method, the method comprising:

providing a substrate containing a first material containing a first surface and a second material containing a second surface, where the second surface contains a metal-containing catalyst layer; and

in the absence of any oxidizing and hydrolyzing agent, exposing the substrate at a substrate temperature of approximately 150°

C. or less, to a process gas containing a silanol gas to selectively deposit a SiO₂ film on the second surface.

14. The method of claim 13, wherein the silanol gas is selected from the group consisting of tris(tert-pentoxy) silanol, tris(tert-butoxy) silanol, and bis(tert-butoxy)(isopropoxy) silanol.

15. The method of claim 13, wherein the metal-containing catalyst layer contains aluminum, titanium, or a combination thereof.

16. The method of claim 13, wherein the metal-containing catalyst layer is selected from the group consisting of Al, Al₂O₃, AlN, AlON, an Al-containing precursor, Al-alloys, CuAl, TiAlN, TaAlN, Ti, TiAlC, TiO₂, TiON, TiN, a Ti-containing precursor, Ti-alloys, and combinations thereof.

17. The method of claim 13, wherein the first material is selected from the group consisting of silicon, germanium, silicon germanium, a dielectric material, a metal, and a metal-containing material.

18. The method of claim 17, wherein the dielectric material is selected from the group consisting of SiO₂, SiON, SiN, a high-k material, a low-k material, and an ultra-low-k material.

19. The method of claim 13, wherein the substrate temperature is approximately 100°

C. or less, during the exposing.

20. The method of claim 13, wherein the process gas consists of a silanol gas and an inert gas.