SEMICONDUCTOR PACKAGE STRUCTURE, PACKAGE ON PACKAGE STRUCTURE AND PACKAGING METHOD

• US 20170294389A1
• Filed: 04/07/2017
• Published: 10/12/2017
• Est. Priority Date: 04/07/2016
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: FACTOR, Bradford, RICE, Rich, GERBER, Mark
• Granted Patent: US 10,177,099 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 23/3735 : Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor package structure includes a substrate, a first semiconductor device, a first encapsulant and a second encapsulant. The substrate has a first coefficient of thermal expansion CTE1. The first semiconductor device is disposed adjacent to a first surface of the substrate. The first encapsulant is disposed on the first surface of the substrate, and covers at least a portion of the first semiconductor device. The first encapsulant has a second coefficient of thermal expansion CTE2. The second encapsulant is disposed on a second surface of the substrate and has a third coefficient of thermal expansion CTE3. A difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3.

Claims

1. A semiconductor package structure, comprising:

a substrate having a first surface and a second surface opposite to the first surface and a first coefficient of thermal expansion CTE1;

a first semiconductor device disposed adjacent to the first surface of the substrate;

a first encapsulant disposed on the first surface of the substrate, covering at least a portion of the first semiconductor device, and having a second coefficient of thermal expansion CTE2; and

a second encapsulant disposed on the second surface of the substrate and having a third coefficient of thermal expansion CTE3,

wherein a difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3.

2. The semiconductor package structure according to claim 1, wherein

0. 9*|CTE3−

CTE1|≦

|CTE2−

CTE1|≦

1.1*|CTE3−

CTE1|.

3. The semiconductor package structure according to claim 1, wherein CTE2 is substantially equal to CTE3.

4. The semiconductor package structure according to claim 3, wherein

|(CTE3−

CTE2)/(CTE3+CTE2)|≦

0.1.

5. The semiconductor package structure according to claim 3, wherein CTE2 is substantially equal to CTE1.

6. The semiconductor package structure according to claim 5, wherein

|(CTE2−

CTE1)/(CTE2+CTE1)|≦

0.1.

7. The semiconductor package structure according to claim 1, wherein the first semiconductor device has a fourth coefficient of thermal expansion CTE4, and CTE4 is substantially equal to CTE1.

8. The semiconductor package structure according to claim 1, further comprising a second semiconductor device disposed adjacent to the second surface of the substrate and having a fifth coefficient of thermal expansion CTE5, wherein the second encapsulant covers at least a portion of the second semiconductor device, and CTE5 is substantially equal to CTE1.

9. The semiconductor package structure according to claim 1, wherein the substrate comprises a first connection pad disposed adjacent to the first surface of the substrate and a second connection pad disposed adjacent to the second surface of the substrate, the first connection pad is exposed from the first encapsulant, and the second connection pad is exposed from the second encapsulant.

10. The semiconductor package structure according to claim 1, wherein the substrate comprises a first connection pad disposed adjacent to the first surface of the substrate, a first intermediate material disposed on the first connection pad, a second connection pad disposed adjacent to the second surface of the substrate and a second intermediate material disposed on the second connection pad, wherein the first intermediate material is exposed from the first encapsulant and the second intermediate material is exposed from the second encapsulant.

11. The semiconductor package structure according to claim 1, wherein a side surface of the first encapsulant, a side surface of the second encapsulant and a lateral surface of the substrate are substantially coplanar.

12. The semiconductor package structure according to claim 1, wherein a thickness of the first encapsulant is substantially equal to a thickness of the second encapsulant.

13. A package on package structure, comprising:

a bottom package, comprising;

a bottom substrate having a first surface and a second surface opposite to the first surface and having a first coefficient of thermal expansion CTE1;

a first semiconductor device disposed adjacent to the first surface of the bottom substrate;

a first encapsulant disposed on the first surface of the bottom substrate, covering at least a portion of the first semiconductor device, and having a second coefficient of thermal expansion CTE2; and

a second encapsulant disposed on the second surface of the bottom substrate and having a third coefficient of thermal expansion CTE3, wherein a difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3; and

a top package disposed on and electrically connected to the bottom package, and comprising;

a top substrate having a first surface and a second surface opposite to the first surface, and having a sixth coefficient of thermal expansion CTE6;

a top semiconductor device disposed adjacent to the first surface of the top substrate; and

a top encapsulant disposed on the first surface of the top substrate, covering at least a portion of the top semiconductor device, and having a seventh coefficient of thermal expansion CTE7, wherein CTE7 is substantially equal to CTE6.

14. The package on package structure according to claim 13, wherein

|(CTE7−

CTE6)/(CTE7+CTE6)|≦

0.1.

15. The package on package structure according to claim 13, wherein CTE7 is substantially equal to CTE2, and CTE6 is substantially equal to CTE1.

16. The package on package structure according to claim 13, wherein the top semiconductor device has an eighth coefficient of thermal expansion CTE8, and CTE8 is substantially equal to CTE6.

17. The package on package structure according to claim 13, wherein a side surface of the first encapsulant, a side surface of the second encapsulant, a lateral surface of the bottom substrate, a side surface of the top encapsulant and a lateral surface of the top substrate are substantially coplanar.

18. A packaging method, comprising:

providing a substrate having a first surface and a second surface opposite to the first surface, and having a first coefficient of thermal expansion CTE1;

mounting a first semiconductor device on the first surface of the substrate;

disposing a first encapsulant on the first surface of the substrate and a second encapsulant on the second surface of the substrate, wherein the first encapsulant covers at least a portion of the first semiconductor device and has a second coefficient of thermal expansion CTE2, the second encapsulant has a third coefficient of thermal expansion CTE3, and a difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3; and

defining a first opening corresponding to a first connection pad disposed adjacent to the first surface of the substrate and a second opening corresponding to a second connection pad disposed adjacent to the second surface of the substrate.

19. The packaging method according to claim 18, wherein the substrate defines a through hole extending therethrough, and disposing the first encapsulant on the first surface of the substrate and the second encapsulant on the second surface of the substrate comprises:

providing a first mold chase and a second mold chase, wherein the substrate is sandwiched between the first mold chase and the second mold chase, the first mold chase defines a first cavity, the second mold chase defines a second cavity, and the first cavity is in communication with the second cavity through the through hole;

applying an overall encapsulant to the first cavity to form the first encapsulant and to the second cavity to form the second encapsulant, wherein the overall encapsulant flows through the through hole; and

removing the first mold chase and the second mold chase.

20. The packaging method according to claim 18, wherein after mounting the first semiconductor device on the first surface of the substrate, the method further comprises:

mounting a second semiconductor device on the second surface of the substrate, wherein the second encapsulant covers at least a portion of the second semiconductor device.

21. The packaging method according to claim 18, wherein the substrate comprises a first connection pad disposed adjacent to the first surface of the substrate and a second connection pad disposed adjacent to the second surface of the substrate, and the first opening exposes the first connection pad and the second opening exposes the second connection pad.

22. The packaging method according to claim 18, wherein the substrate comprises a first connection pad disposed adjacent to the first surface of the substrate, a first intermediate material disposed on the first connection pad, a second connection pad disposed adjacent to the second surface of the substrate and a second intermediate material disposed on the second connection pad, and wherein the first opening exposes the first intermediate material and the second opening exposes the second intermediate material.