DISPLAY APPARATUS AND METHOD OF MANUFACTURING DISPLAY APPARATUS

• US 20170294502A1
• Filed: 01/12/2017
• Published: 10/12/2017
• Est. Priority Date: 04/12/2016
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: KA, JI-HYUN, LEE, SEUNG-KYU, JANG, HWAN-SOO, JEONG, JIN-TAE
• Granted Patent: US 10,134,826 B2
• Time in Patent Office: Days
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/121 characterised by the geometry or disposition of pixel elements
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass

Abstract

A display apparatus includes a substrate including a display area, a peripheral area surrounding the display area, a function-adding area, of which at least a portion is surrounded by the display area, and a detour area disposed between the display area and the function-adding area. The display apparatus includes a plurality of pixel circuits disposed in the display area. A plurality of driving lines are electrically connected to the pixel circuits and extend in a direction in the display area. A first detour line is disposed in the detour area and is electrically connected to a first driving line. A second detour line is disposed in the detour area. The second detour line is electrically connected to a second driving line and is disposed in a different layer from the first detour line.

Claims

1. A display apparatus comprising:

a substrate including a display area, a peripheral area surrounding the display area, a function-adding area, of which at least a portion is surrounded by the display area, and a detour area disposed between the display area and the function-adding area;

a plurality of pixel circuits disposed in the display area;

a plurality of driving lines electrically connected to the pixel circuits and extending in a first direction in the display area;

a first detour line disposed in the detour area and electrically connected to a first driving line; and

a second detour line disposed in the detour area and electrically connected to a second driving line and disposed in a different layer from the first detour line.

2. The display apparatus of claim 1, wherein the first and second detour lines are adjacent to an edge of the function-adding area in a plan view.

3. The display apparatus of claim 1, wherein the first and second detour lines are alternatingly arranged in a second direction crossing the first direction.

4. The display apparatus of claim 1, wherein the driving lines include data lines.

5. The display apparatus of claim 4, further comprising:

a scan line electrically connected to the pixel circuits in the display area and extending in a second direction crossing the first direction; and

a third detour line electrically connected to the scan line and disposed in the detour area.

6. The display apparatus of claim 5, wherein the third detour line is disposed in a different layer from the scan line.

7. The display apparatus of claim 6, wherein the scan line includes a first portion and a second portion spaced apart from the first portion by the detour area, and wherein the third detour line electrically connects the first portion to the second portion.

8. The display apparatus of claim 5, wherein the scan line is electrically connected to a gate electrode of a switching transistor that receives a data signal through at least one of the data lines.

9. The display apparatus of claim 5, further comprising:

a power line electrically connected to the pixel circuits and extending in the first direction in the display area;

a power bus line extending in the second direction in the peripheral area; and

a detour bus line disposed in the detour area and electrically connecting the power line to the power bus line.

10. The display apparatus of claim 9, wherein the detour bus line is adjacent to an edge of the function-adding area in a plan view.

11. The display apparatus of claim 10, wherein the power bus line includes a first portion and a second portion spaced apart from the first portion by the detour area, and wherein the detour bus line electrically connects the first portion to the second portion.

12. The display apparatus of claim 9, further comprising an insulation structure that covers the pixel circuits and is disposed in the display area and the detour area, the insulation structure comprising a gate insulation layer, an interlayer insulation layer and a via insulation layer, which are sequentially disposed above the substrate,

wherein each of the pixel circuits comprises:

an active pattern disposed under the gate insulation layer;

a gate electrode disposed on the gate insulation layer and overlapping the active pattern;

a source electrode disposed on the interlayer insulation layer and electrically connected to the active pattern;

a drain electrode spaced apart from the source electrode; and

a pixel electrode disposed on the via insulation layer and electrically connected to the drain electrode.

13. The display apparatus of claim 12, wherein the gate insulation layer includes a first gate insulation layer and a second insulation layer disposed on the first gate insulation layer, and

wherein the first detour line is disposed on the first gate insulation layer, and the second detour line is disposed on the second gate insulation layer.

14. The display apparatus of claim 12, wherein the third detour line is disposed between the interlayer insulation layer and the via insulation layer.

15. The display apparatus of claim 14, wherein the detour bus line is disposed on the via insulation layer.

16. The display apparatus of claim 9, wherein the first and second detour lines extend into the peripheral area and cross the power bus line.

17. The display apparatus of claim 4, further comprising:

a power line electrically connected to the pixel circuits and extending in the first direction in the display area;

a power bus line extending in the second direction in the peripheral area;

a detour bus line disposed in the detour area and electrically connecting the power line to the power bus line; and

an insulation structure that covers the pixel circuits and is disposed in the display area and the detour area, the insulation structure comprising a gate insulation layer, an interlayer insulation layer and a via insulation layer, which are sequentially disposed above the substrate,

wherein the power line, the power bus line and the detour bus line are disposed between the interlayer insulation layer and the via insulation layer.

18. The display apparatus of claim 1, wherein the function-adding area is defined by an opening passing through the substrate.

19. The display apparatus of claim 1, further comprising a light-emitting layer electrically connected to the pixel circuits.

20. A method for manufacturing a display apparatus, the method comprising:

forming a first gate pattern including a first detour line and a scan line on a substrate;

forming a gate insulation layer that covers the first gate pattern;

forming a second gate pattern including a second detour line on the gate insulation layer;

forming an interlayer insulation layer that covers the second gate pattern;

forming a source pattern on the interlayer insulation layer, the source pattern including a first data line electrically connected to the first detour line, a second data line electrically connected to the second detour line, and a third detour line electrically connected to the scan line and crossing the first detour line and the second detour line; and

forming a via insulation layer that covers the source pattern.

21. The method of claim 20, wherein the substrate includes a function-adding area defined by an opening passing through the substrate, and

wherein the first to third detour lines are adjacent to an edge of the function-adding area in a plan view.

22. The method of claim 20, wherein the source pattern further includes:

a power line extending in a same direction as the data lines; and

a power bus line extending in a direction crossing the power line and electrically connected to the power line.

23. The method of claim 22, further comprising:

forming a detour bus line on the via insulation layer, the detour bus line electrically connecting the power line to the power bus line.

24. A display apparatus comprising:

a substrate comprising a display area, a peripheral area and a detour area;

a hole formed in the substrate and overlapping a portion of the display area and a portion of the peripheral area, wherein the detour area is adjacent to the hole in the display area;

at least one pixel comprising a pixel circuit disposed in the display area;

a first data line disposed in the display area;

a second data line disposed in the display area;

a first detour line disposed in the detour area and electrically connected to the first data line;

a second detour line disposed in the detour area and electrically connected to the second data line, wherein the first and second detour lines are disposed in different layers from each other;

a first power voltage line disposed in the peripheral area, wherein the first power voltage line comprises a first portion disposed on a first side of the detour area and a second portion disposed on a second side of the detour area opposite the first side of the detour area; and

a detour bus line disposed in the detour area, wherein the detour bus line connects the first portion of the first power voltage line with the second portion of the first power voltage line.

25. The display apparatus of claim 24, wherein the pixel circuit of the at least one pixel comprises:

an active pattern disposed under the gate insulation layer;

a gate electrode disposed on the gate insulation layer and overlapping the active pattern;

a source electrode disposed on the interlayer insulation layer and electrically connected to the active pattern;

a drain electrode spaced apart from the source electrode; and

a pixel electrode disposed on the via insulation layer and electrically connected to the drain electrode.

26. The display apparatus of claim 24, wherein the first and second data lines extend in a first direction, and wherein the first and second portions of the first power voltage line extend in a second direction perpendicular to the first direction.

27. The display apparatus of claim 24, further comprising:

a scan line electrically connected to the pixel circuit of the at least one pixel in the display area; and

a third detour line electrically connected to the scan line and disposed in the detour area.

28. The display apparatus of claim 27, wherein the third detour line is disposed on a different level from the first detour line.