Decision Feedback Equalizer

• US 20170295040A1
• Filed: 04/27/2017
• Published: 10/12/2017
• Est. Priority Date: 02/23/2010
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Leibowitz, Brian S., Kim, Jaeha
• Granted Patent: US 10,397,028 B2
• Time in Patent Office: Days
• CPC Class Codes: H03M 1/004 Reconfigurable analogue/digital or digital/analogue converters H03M1/02 takes precedence
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H03M 1/362 the reference values being generated by a resistive voltage divider
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/03369 Partial response
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03146 with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

Claims

1. (canceled)

2. An equalizer comprising:

M samplers to sample an analog signal during a given symbol time, each of the M samplers to sample the analog signal with respect to a corresponding one of a range of sample instants and a corresponding one of a range of reference levels to produce M speculative samples;

select logic to convey a selected one of the M speculative samples as a presently resolved bit; and

storage to store N previously resolved bits, where 2̂

N is less than M;

the select logic to select the presently resolved bit based on a correspondence between the N previously resolved bits and the M speculative samples.

3. The equalizer of claim 2, wherein the select logic is programmable to program the correspondence between the N previously resolved bits and the M speculative samples.

4. The equalizer of claim 3, wherein the select logic is externally programmable to define how the select logic defines the correspondence between the N previously resolved bits and the M speculative samples.

5. The equalizer of claim 3, wherein the select logic is externally programmable to define a second correspondence between each possible pattern of the N previously resolved bits and one of the M speculative samples.

6. The equalizer of claim 2, the storage to store a total number of previously resolved bits that is more than the N previously resolved bits, the equalizer further including a decoder to select the N previously resolved bits from the total number of previously resolved bits.

7. The equalizer of claim 2, further comprising a cross-bar switch interconnecting the samplers with the select logic.

8. The equalizer of claim 2, wherein the select logic further includes a decoder and a multiplexer, the decoder to decode the N previously resolved bits into a decoder output, the multiplexer to produce the presently resolved bit from the M speculative samples in response to the decoder output.

9. The equalizer of claim 2, wherein the select logic conveys the same selected one of the M speculative samples as the presently resolved bit responsive to more than one pattern of the N previously resolved bits.

10. The equalizer of claim 2, further comprising a second ADC to sample the analog signal during a second symbol time to produce M additional speculative samples.

11. The equalizer of claim 10, further comprising second select logic coupled to the second ADC to select a second presently resolved bit for the second symbol time from the additional speculative samples.

12. A method of equalizing an analog signal, the method comprising:

sampling the analog signal during previous symbol times to obtain N previously resolved bits;

storing the N previously resolved bits in storage;

sampling the analog signal during a present symbol time with respect to M references and M phases to obtain M speculative samples;

selecting one of the M speculative samples as a presently resolved bit using select logic defining a correspondence between the N previously resolved bits and the M speculative samples;

storing the presently resolved bit in the storage as a most-recent previously resolved bit; and

varying ones of the M phases relative to one another to select preferred sample instants.

13. The method of claim 12, further comprising programming the correspondence between the N previously resolved bits and the selected one of the M speculative samples.

14. The method of claim 12, further comprising sampling the analog signal using alternative analog-to-digital converters during adjacent symbol times to obtain adjacent groups of speculative samples.

15. The method of claim 14, further comprising selecting a speculative sample from one of the alternative analog-to-digital converters as the presently resolved bit using a previously resolved bit from the other of the analog-to-digital converters.

16. The method of claim 12, further comprising storing more than the N previously resolved bits in the storage and programmably selecting the N previously resolved bits from the storage.

17. An equalizer comprising:

an analog-to-digital converter (ADC) to sample an analog signal with respect to M references and M phases during a symbol time to produce M speculative samples;

means for decoding N previously resolved samples of the analog signal to select one of the M speculative samples, wherein M is not 2̂

N, and wherein the means for decoding provides a programmable correspondence between the N previously resolved samples and the M speculative samples; and

means for updating the previously resolved samples to include the selected one of the M speculative samples.

18. The equalizer of claim 17, wherein the means for decoding the N previously resolved samples programmably selects the N previously resolved samples from a greater number of previously resolved samples.

19. The equalizer of claim 17, further comprising means for changing the correspondence between the previously resolved samples and the M speculative samples.

20. The equalizer of claim 17, wherein M is less than 2̂

N.