POWER MANAGEMENT CIRCUIT AND ASSOCIATED POWER MANAGEMENT METHOD

• US 20170300077A1
• Filed: 07/04/2017
• Published: 10/19/2017
• Est. Priority Date: 09/29/2014
• Status: Abandoned Application

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Hsu, Chia-Tao, Ung, Chee-Kong, Yang, Li-Chun, Chen, Yu-Sung, Dai, Ming-Tse
• Application Number:
  US15/641,233
• Publication Number:
  US 20170300077A1
• Time in Patent Office: Days
• CPC Class Codes: G01R 19/0084 measuring voltage only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G05F 3/04 wherein the variable is ac

Abstract

A power management circuit includes a voltage sensing circuit and a supply voltage adjusting circuit. The voltage sensing circuit is arranged for sensing a plurality of voltages respectively of a plurality of nodes of a PCB to generate a sensing result. The supply voltage adjusting circuit is coupled to the voltage sensing circuit, and is arranged for determining a voltage level of a supply voltage supplied to a power plane of the PCB by referring to the sensing result.

Claims

1. A power management circuit, comprising:

a voltage sensing circuit, for sensing a plurality of voltages respectively of a plurality of nodes of a printed circuit board (PCB) to generate a sensing result; and

a supply voltage adjusting circuit, coupled to the voltage sensing circuit, for determining a voltage level of a supply voltage supplied to a power plane of the PCB by referring to the sensing result.

2. The power management circuit of claim 1, wherein the PCB has a plurality of integrated circuits (ICs) mounted thereon, the power plane of the PCB is shared by the ICs, and the voltage sensing circuit senses voltage levels of the supply voltage received by the ICs, respectively, to generate the sensing result.

3. The power management circuit of claim 1, wherein the PCB has a plurality of ICs mounted thereon, the power plane of the PCB is shared by the ICs, and the voltage sensing circuit senses voltage levels close to at least a portion of the ICs to generate the sensing result.

4. The power management circuit of claim 1, wherein the sensing result is information about a lowest voltage among the voltages of the nodes of the PCB.

5. The power management circuit of claim 1, wherein the sensing result is information about an average of the voltages of the nodes of the PCB.

6. The power management circuit of claim 1, wherein the voltage sensing circuit receives the plurality of voltages of the nodes of the PCB, and the sensing result is generated according to only a portion of the sensed voltages.

7. The power management circuit of claim 1, wherein the supply voltage adjusting circuit is built in a power management integrated circuit (PMIC), and the voltage sensing circuit is built in a chip external to the PMIC.

8. A power management method, comprising:

sensing a plurality of voltages respectively of a plurality of nodes of a printed circuit board (PCB) to generate a sensing result; and

determining a voltage level of a supply voltage supplied to a power plane of the PCB by referring to the sensing result.

9. The power management method of claim 8, wherein the PCB has a plurality of integrated circuits (ICs) mounted thereon, the power plane of the PCB is shared by the ICs, and the step of generating the sensing result comprises:

sensing voltage levels of the supply voltage received by the ICs, respectively, to generate the sensing result.

10. The power management method of claim 8, wherein the PCB has a plurality of ICs mounted thereon, the power plane of the PCB is shared by the ICs, and the step of generating the sensing result comprises:

sensing voltage levels close to at least a portion of the ICs to generate the sensing result.

11. The power management method of claim 8, wherein the sensing result is information about a lowest voltage among the voltages of the nodes of the PCB.

12. The power management method of claim 8, wherein the sensing result is information about an average of the voltages of the nodes of the PCB.

13. The power management method of claim 8, the step of generating the sensing result comprises:

filtering the voltages of the nodes of the PCB;

performing analog-to-digital converting operations upon filtered voltages to generate digital form of the filtered voltages; and

generating the sensing result according to the digital form of the filtered voltages.

14. The power management method of claim 8, wherein the sensing result is generated according to only a portion of the sensed voltages.

15. A power management method, comprising:

obtaining operation statuses of a plurality of integrated circuits (ICs) mounted on a printed circuit board (PCB) to generate a determining result; and

determining a voltage level of a supply voltage supplied to a power plane of the PCB by referring to the determining result.

16. The power management method of claim 15, wherein the operation status of each IC is an active status or inactive status of the IC.

17. The power management method of claim 15, wherein the step of determining the voltage level of the supply voltage comprises:

determining the voltage level of the supply voltage by using a look-up table, wherein the look-up table records combinations of the operation statuses of the ICs and corresponding voltage levels.

18. The power management method of claim 17, wherein the look-up table is built off-line.

19. The power management method of claim 17, wherein the operation status of each IC is an active status or inactive status of the IC.

20. The power management method of claim 15, wherein the determining step is performed by a microprocessor, and the power management method further comprises:

transmitting information about the determining voltage level of the supply voltage from the microprocessor to a power management integrated circuit (PMIC) to adjust the supply voltage supplied to the power plane of the PCB.