SYSTEMS AND METHODS FOR ADAPTIVE CLOCK DESIGN

• US 20170300080A1
• Filed: 04/19/2016
• Published: 10/19/2017
• Est. Priority Date: 04/19/2016
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: JAIN, Palkesh, BANSAL, Virendra, MEHROTRA, Manoj, BOWMAN, Keith Alan
• Granted Patent: US 9,915,968 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/305 in the event of power-supply fluctuations
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop

Abstract

The present disclosure is directed to mitigating voltage droops. An aspect includes outputting, by a clock module coupled to a multiplexor, a first clock signal to the multiplexor, the first clock signal generated by a clock delay component of the clock module, receiving, by the clock module, a second clock signal from a phase-locked loop (PLL), wherein the PLL outputs a third clock signal to a processor coupled to the PLL and the multiplexor, selecting, by the multiplexor, the first clock signal to output to the processor based on detecting a droop in voltage on a power supply, and selecting, by the multiplexor, the third clock signal to output to the processor based on detecting that the droop in the voltage on the power supply has passed, wherein the clock module and the processor are coupled to the power supply.

Claims

1. An apparatus for mitigating voltage droops, comprising:

a processor coupled to a first power supply;

a multiplexor coupled to the processor;

a clock module coupled to the multiplexor and the first power supply, wherein the clock module includes a clock delay component; and

a phase-locked loop (PLL) coupled to the multiplexor,

wherein the clock module outputs a first clock signal to the multiplexor and receives a second clock signal from the PLL, the first clock signal generated by the clock delay component,

wherein the multiplexor is configured to select the first clock signal from the clock module or a third clock signal from the PLL to output to the processor, and

wherein, based on detection of a first droop in voltage on the first power supply, the multiplexor selects the first clock signal from the clock module to output to the processor.

2. The apparatus of claim 1, wherein the PLL is coupled to a second power supply different from the first power supply.

3. The apparatus of claim 1, wherein the clock delay component comprises a ring oscillator.

4. The apparatus of claim 1, wherein the clock delay component slows down a frequency of the first clock signal in response to detection of the first droop in the voltage on the first power supply.

5. The apparatus of claim 1, wherein the clock delay component includes a plurality of delay elements, and wherein each delay element of the plurality of delay elements, when selected, delays the first clock signal by a delay amount equal to the delay amount of each remaining delay element of the plurality of delay elements.

6. The apparatus of claim 5, wherein a number of the plurality of delay elements selected is based on the second clock signal from the PLL, and wherein the second clock signal is based on a user configuration.

7. The apparatus of claim 1, wherein the clock module detects and responds to the first droop in the voltage in real-time based on the clock module and the processor being connected to the first power supply.

8. The apparatus of claim 1, wherein, based on detection that the first droop in the voltage on the first power supply has passed, the multiplexor selects the third clock signal from the PLL.

9. The apparatus of claim 1, wherein a delay of the clock delay component is calibrated to a frequency of the PLL.

10. The apparatus of claim 9, wherein the calibration is performed in real time, at periodic intervals, upon one or more trigger conditions, based on a user triggering a mode change of a user device including the processor, or any combination thereof.

11. The apparatus of claim 10, wherein the user triggering the mode change comprises the user switching a mode of operation of the user device from a first mode to a second mode, wherein the second mode utilizes a lower frequency of the processor than the first mode.

12. The apparatus of claim 1, wherein a second droop in the voltage detected on the first power supply, the second droop in the voltage in a different frequency spectrum than the first droop in the voltage, and

wherein the first power supply is coupled to one or more filters configured to bypass the second droop in the voltage based on the second droop in the voltage being in the different frequency spectrum.

13. A method of mitigating voltage droops, comprising:

outputting, by a clock module coupled to a multiplexor, a first clock signal to the multiplexor, the first clock signal generated by a clock delay component of the clock module;

receiving, by the clock module, a second clock signal from a phase-locked loop (PLL), wherein the PLL outputs a third clock signal to a processor coupled to the PLL and the multiplexor;

selecting, by the multiplexor, the first clock signal to output to the processor based on detecting a first droop in voltage on a first power supply; and

selecting, by the multiplexor, the third clock signal to output to the processor based on detecting that the first droop in the voltage on the first power supply has passed,

wherein the clock module and the processor are coupled to the first power supply.

14. The method of claim 13, wherein the PLL is coupled to a second power supply different from the first power supply.

15. The method of claim 13, wherein the clock delay component comprises a ring oscillator.

16. The method of claim 13, wherein the clock delay component slows down a frequency of the first clock signal in response to detection of the first droop in the voltage on the first power supply.

17. The method of claim 13, wherein the clock delay component includes a plurality of delay elements, and wherein each delay element of the plurality of delay elements, when selected, delays the first clock signal by a delay amount equal to the delay amount of each remaining delay element of the plurality of delay elements.

18. The method of claim 17, wherein a number of the plurality of delay elements selected is based on the second clock signal from the PLL, and wherein the second clock signal is based on a user configuration.

19. The method of claim 13, wherein the clock module detects and responds to the first droop in the voltage in real-time based on the clock module and the processor being connected to the first power supply.

20. The method of claim 13, wherein, based on detecting that the first droop in the voltage on the first power supply has passed, the multiplexor selects the third clock signal from the PLL.

21. The method of claim 13, wherein a delay of the clock delay component is calibrated to a frequency of the PLL.

22. The method of claim 21, wherein the calibration is performed in real time, at periodic intervals, upon one or more trigger conditions, based on a user triggering a mode change of a user device including the processor, or any combination thereof.

23. The method of claim 22, wherein the user triggering the mode change comprises the user switching a mode of operation of the user device from a first mode to a second mode, wherein the second mode utilizes a lower frequency of the processor than the first mode.

24. The method of claim 13, further comprising:

detecting a second droop in the voltage on the first power supply, wherein the second droop in the voltage is in a different frequency spectrum than the first droop in the voltage, and

bypassing, by one or more filters coupled to the first power supply, the second droop in the voltage based on the second droop in the voltage being in the different frequency spectrum.

25. An apparatus for mitigating voltage droops, comprising:

a processor means coupled to a first power supply means;

a multiplexor means coupled to the processor means;

a clock means coupled to the multiplexor means and the first power supply means, wherein the clock means includes a clock delay component; and

a phase-locked loop (PLL) coupled to the multiplexor means,

wherein the clock means outputs a first clock signal to the multiplexor means and receives a second clock signal from the PLL, the first clock signal generated by the clock delay component,

wherein the multiplexor means is configured to select the first clock signal from the clock means or a third clock signal from the PLL to output to the processor means, and

wherein, based on detection of a droop in voltage on the first power supply means, the multiplexor means selects the first clock signal from the clock means to output to the processor means.

26. The apparatus of claim 25, wherein the PLL is coupled to a second power supply different from the first power supply.

27. The apparatus of claim 25, wherein the clock means detects and responds to the droop in the voltage in real-time based on the clock means and the processor being connected to the first power supply.

28. A non-transitory computer-readable medium for mitigating voltage droops, comprising:

at least one instruction to output, by a clock module coupled to a multiplexor, a first clock signal to the multiplexor, the first clock signal generated by a clock delay component of the clock module;

at least one instruction to receive, by the clock module, a second clock signal from a phase-locked loop (PLL), wherein the PLL outputs a third clock signal to a processor coupled to the PLL and the multiplexor;

at least one instruction to select, by the multiplexor, the first clock signal to output to the processor based on detecting a droop in voltage on a first power supply; and

at least one instruction to select, by the multiplexor, the third clock signal to output to the processor based on detection that the droop in the voltage on the first power supply has passed,

wherein the clock module and the processor are coupled to the first power supply.

29. The non-transitory computer-readable medium of claim 28, wherein the PLL is coupled to a second power supply different from the first power supply.

30. The non-transitory computer-readable medium of claim 28, wherein the clock module detects and responds to the droop in the voltage in real-time based on the clock module and the processor being connected to the first power supply.