SYSTEMS AND METHODS FOR IMPROVING EFFICIENCIES OF A MEMORY SYSTEM

• US 20170300382A1
• Filed: 06/29/2017
• Published: 10/19/2017
• Est. Priority Date: 06/02/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pawlowski, J. Thomas
• Granted Patent: US 10,572,164 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/07 Responding to the occurrence of a fault, e.g. fault tolerance
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0617 in relation to availability
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 : Single storage device
• CPC Class Codes: G06F 3/0679 : Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0683 : Plurality of storage devices
• CPC Class Codes: G06F 3/0685 : Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H04L 1/189 : Transmission or retransmission of more than one copy of a message
• CPC Class Codes: H04L 47/12 : Avoiding congestion; Recovering from congestion
• CPC Class Codes: H04L 47/25 : with rate being modified by the source upon detecting a change of network conditions
• CPC Class Codes: H04L 47/52 : by attributing bandwidth to queues
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory device includes a memory component that stores data. The memory device also includes a processor that receives a signal indicating that the memory component is coupled to the processor and retrieves information from the memory component. The information may include one or more algorithms capable of being performed by the memory component. The processor may then receive one or more packets associated with one or more data operations regarding the memory component. The processor may then perform the one or more data operations by using the memory component to employ the one or more algorithms.

Claims

1. A memory device comprising:

a memory component configured to store data; and

a processor, configured to;

receive a signal indicating that the memory component is coupled to the processor;

retrieve information from the memory component, wherein the information comprises one or more locations within the memory component in which one or more operations are to be performed by the memory component;

receive one or more packets associated with one or more data operations regarding the memory component; and

perform the one or more data operations at the one more locations of the memory component.

2. The memory device of claim 1, wherein the signal is received upon receiving power at the processor.

3. The memory device of claim 1, wherein the information comprises an indication regarding whether the memory device is capable of performing a portion of the one or more data operations.

4. The memory device of claim 1, wherein the memory component comprises a Dynamic Random-Access Memory, a Static Random-Access Memory, a NAND memory, or any combination thereof.

5. The memory device of claim 1, wherein the information comprises an amount of memory space in the memory device.

6. A system, comprising:

a memory device comprising a processor; and

a first component, configured to;

receive a packet associated with a data operation to send to the processor from a second component, wherein the packet comprises;

a transaction type field comprising a number of bits in an error control code;

a payload field comprising a payload; and

an error control code field comprising the error control code

configured to verify an authenticity of the payload;

determine a type of error control code algorithm to employ based on the amount of bits; and

decode the packet based on the type of error control code algorithm.

7. The system of claim 6, wherein the first component is configured to:

determine a number of errors associated with decoding the packet based on the type of error control code algorithm; and

decode the packet using a second type of error control algorithm in response to the number of errors being above a threshold.

8. The system of claim 6, wherein the number of bits is directly proportional to a size of the payload.

9. The system of claim 6, wherein the type of error control algorithm comprises error control code comprises a Hamming Distance 3 (HD3) error control code, a Hamming Distance 4 (HD4) error control code, a Hamming Distance 5 (HD5) error control code, a Hamming Distance 6 (HD6) error control code, a Hamming Distance 7 (HD7) error control code, or a Hamming Distance 8 (HD8) error control code.

10. The system of claim 9, wherein the HD3 error control code is configured to detect every 1-bit and 2-bit error in the payload.

11. The system of claim 9, wherein the HD4 error control code is configured to detect every 1-bit, 2-bit error, and 3-bit error in the payload.

12. The system of claim 9, wherein the HD5 error control code is configured to detect every 1-bit, 2-bit error, 3-bit error, and 4-bit error in the payload.

13. The system of claim 9, wherein the HD6 error control code is configured to detect every 1-bit, 2-bit error, 3-bit error, 4-bit error, and 5-bit error in the payload.

14. The system of claim 9, wherein the HD7 error control code is configured to detect every 1-bit, 2-bit error, 3-bit error, 4-bit error, 5-bit error, and 6-bit error in the payload.

15. The system of claim 9, wherein the HD8 error control code is configured to detect every 1-bit, 2-bit error, 3-bit error, 4-bit error, 5-bit error, 6-bit error, and 7-bit error in the payload.

16. A tangible, non-transitory, machine-readable medium, comprising instructions configured to:

receive a plurality of packets from a plurality of control silicons associated with one or more memory components, wherein the plurality of packets is associated with a plurality of data operations to be performed on a memory component of the one or more memory components, and wherein each of the plurality of packets comprises a source field indicative of a source of a respective packet and a destination field indicative of a destination of the respective packet; and

perform one or more data operations using the memory component based on the plurality of packets.

17. The tangible, non-transitory, machine-readable medium of claim 16, wherein each of the plurality of control silicons is associated with a system window comprising a virtual channel implemented using a virtual address space associated with the memory component.

18. The tangible, non-transitory, machine-readable medium of claim 17, wherein the instructions are configured to generate a globally-enabled memory management system based on the system window for each of the plurality of control silicons.

19. The tangible, non-transitory, machine-readable medium of claim 18, wherein the globally-enabled memory management system comprises a mapping between virtual memory space comprising the virtual address space to an actual memory space of the memory component.

20. The tangible, non-transitory, machine-readable medium of claim 17, wherein the globally-enabled memory management system comprises an access list indicative of a portion of the plurality of control silicons that is provided access to the memory component.