GATE ON ARRAY (GOA) UNIT, GATE DRIVER CIRCUIT AND DISPLAY DEVICE

• US 20170301277A1
• Filed: 02/18/2016
• Published: 10/19/2017
• Est. Priority Date: 09/23/2015
• Status: Abandoned Application

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: SHANG GUAN, XINGCHEN
• Application Number:
  US15/324,881
• Publication Number:
  US 20170301277A1
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET

Abstract

A gate on array (GOA) unit, a gate driver circuit, and a display device are provided. The GOA unit includes a driver circuit configured to output a first clock signal from an output end of the GOA unit. The GOA unit further includes a pull-down circuit connected with the driver circuit, the pull-down circuit also connected with at least one low-voltage end that provides a low-voltage signal, the pull-down circuit configured to input the low-voltage signal into a control end of the driver circuit to drive the driver circuit to be in an off state when the GOA unit outputs an off signal. The GOA unit can avoid incorrect switching-on of one row of pixels corresponding to the GOA unit, so that the row of pixels cannot be charged and display incorrect images, and hence an “abnormal image” phenomenon can be overcome.

Claims

1. A gate on array (GOA) unit, comprising:

a driver circuit configured to output a first clock signal from an output end of the GOA unit; and

a pull-down circuit connected with the driver circuit, the pull-down circuit also connected with at least one low-voltage end that provides a low-voltage signal, the pull-down circuit configured to input the low-voltage signal into a control end of the driver circuit to drive the driver circuit to be in an off state when the GOA unit outputs an off signal.

2. The GOA unit according to claim 1, wherein the pull-down circuit includes a first sub-circuit, a second sub-circuit and a third sub-circuit;

a first end of the first sub-circuit is connected with the control end of the driver circuit;

a second end of the first sub-circuit is connected with the at least one low-voltage end;

a third end of the first sub-circuit is connected with the second sub-circuit and the third sub-circuit;

a first end of the second sub-circuit is connected with a signal input end;

a second end of the second sub-circuit is connected with a second clock signal;

a third end of the second sub-circuit is connected with the third end of the first sub-circuit;

a first end of the third sub-circuit is connected with the at least one low-voltage end;

a second end of the third sub-circuit is connected with the control end of the driver circuit; and

a third end of the third sub-circuit is connected with the third end of the first sub-circuit.

3. The GOA unit according to claim 2, wherein the pull-down circuit further includes a fourth sub-circuit;

a first end of the fourth sub-circuit is connected with the output end of the GOA unit;

a second end of the fourth sub-circuit is connected with the at least one low-voltage end; and

a third end of the fourth sub-circuit is connected with the third end of the second sub-circuit and the third end of the third sub-circuit.

4. The GOA unit according to claim 2, wherein the second sub-circuit includes a first transistor and a second transistor;

a control electrode of the first transistor is the second end of the second sub-circuit and connected with the second clock signal;

a source electrode of the first transistor is the first end of the second sub-circuit and connected with the signal input end;

a drain electrode of the first transistor is connected with a control electrode and a source electrode of the second transistor;

a drain electrode of the second transistor is the third end of the second sub-circuit and connected with the third end of the first sub-circuit; and

a high voltage signal or the second clock signal is inputted from the signal input end.

5. The GOA unit according to claim 2, wherein the third sub-circuit includes a third transistor;

a control electrode of the third transistor is the second end of the third sub-circuit and connected with the control end of the driver circuit;

a source electrode of the third transistor is the first end of the third sub-circuit and connected with the at least one low-voltage end; and

a drain electrode of the third transistor is the third end of the third sub-circuit and connected with the third end of the first sub-circuit.

6. The GOA unit according to claim 2, wherein the first sub-circuit includes a fourth transistor;

a control electrode of the fourth transistor is the third end of the first sub-circuit and connected with the second sub-circuit and the third sub-circuit;

a source electrode of the fourth transistor is the second end of the first sub-circuit and connected with the at least one low-voltage end; and

a drain electrode of the fourth transistor is the first end of the first sub-circuit and connected with the control end of the driver circuit.

7. The GOA unit according to claim 3, wherein the fourth sub-circuit includes a fifth transistor;

a control electrode of the fifth transistor is the third end of the fourth sub-circuit and connected with the third end of the second sub-circuit and the third end of the third sub-circuit;

a source electrode of the fifth transistor is the second end of the fourth sub-circuit and connected with the at least one low-voltage end; and

a drain electrode of the fifth transistor is the first end of the fourth sub-circuit and connected with the output end of the GOA unit.

8. The GOA unit according to claim 2, wherein the first sub-circuit includes a fourth transistor;

the second sub-circuit includes a first transistor and a second transistor;

the third sub-circuit includes a third transistor;

a control electrode of the first transistor is connected with the second clock signal;

a source electrode of the first transistor is connected with the signal input end;

a drain electrode of the first transistor is connected with a control electrode and a source electrode of the second transistor;

a drain electrode of the second transistor is connected with a control electrode of the fourth transistor;

a control electrode of the third transistor is connected with the control end of the driver circuit;

a source electrode of the third transistor is connected with the at least one low-voltage end;

a drain electrode of the third transistor is connected with a control electrode of the fourth transistor;

a source electrode of the fourth transistor is connected with the at least one low-voltage end;

a drain electrode of the fourth transistor is connected with the control end of the driver circuit; and

a high voltage signal or the second clock signal is inputted from the signal input end.

9. The GOA unit according to claim 8, wherein a low-voltage end connected with the source electrode of the third transistor and a low-voltage end connected with the source electrode of the fourth transistor are a same voltage end.

10. The GOA unit according to claim 8, wherein the pull-down circuit further includes a fourth sub-circuit;

the fourth sub-circuit includes a fifth transistor;

a control electrode of the fifth transistor is connected with the control electrode of the fourth transistor;

a source electrode of the fifth transistor is connected with the at least one low-voltage end; and

a drain electrode of the fifth transistor is connected with the output end of the GOA unit.

11. The GOA unit according to claim 10, wherein a low-voltage end connected with the source electrode of the third transistor, a low-voltage end connected with the source electrode of the fourth transistor, and a low-voltage end connected with the source electrode of the fifth transistor are a same voltage end.

12. The GOA unit according to claim 1, further comprising a pull-up circuit, wherein an output end of the pull-up circuit is connected with the driver circuit so as to input a pull-up signal into the driver circuit;

and the pull-up signal is configured to drive the driver circuit to be switched on.

13. The GOA unit according to claim 12, wherein the driver circuit includes a driving transistor;

a control electrode of the driving transistor is the control end of the driver circuit and connected with the output end of the pull-up circuit;

a source electrode of the driving transistor is connected with the first clock signal; and

a drain electrode of the driving transistor is connected with the output end of the GOA unit.

14. The GOA unit according to claim 12, further comprising a reset circuit, wherein the reset circuit is connected with the driver circuit and configured to input the low-voltage signal into the control end of the driver circuit and the output end of the GOA unit;

and the low-voltage signal is configured to drive the driver circuit to be switched off and pull down a signal outputted by the GOA unit.

15. The GOA unit according to claim 13, wherein the pull-up circuit includes a sixth transistor and a first capacitor;

a control electrode and a source electrode of the sixth transistor are connected with the pull-up signal;

a drain electrode of the sixth transistor is connected with the control electrode of the driving transistor;

a first end of the first capacitor is connected between the drain electrode of the sixth transistor and the control electrode of the driving transistor; and

a second end of the first capacitor is connected with the output end of the GOA unit.

16. The GOA unit according to claim 14, wherein the reset circuit includes an eighth transistor and a ninth transistor;

a control electrode of the eighth transistor is connected with a signal reset end;

a source electrode of the eighth transistor is connected with the at least one low-voltage end;

a drain electrode of the eighth transistor is connected with the control end of the driver circuit;

a control electrode of the ninth transistor is connected with the signal reset end;

a source electrode of the ninth transistor is connected with the at least one low-voltage end; and

a drain electrode of the ninth transistor is connected with the output end of the GOA unit.

17. The GOA unit according to claim 4, wherein the high voltage signal inputted from the signal input end is equal to a turn-on voltage of a gate driver circuit.

18. A gate driver circuit, comprising the GOA unit according to claim 1.

19. A display device, comprising the gate driver circuit according to claim 18.

20. The GOA unit according to claim 3, wherein the second sub-circuit includes a first transistor and a second transistor;

a control electrode of the first transistor is the second end of the second sub-circuit and connected with the second clock signal;

a source electrode of the first transistor is the first end of the second sub-circuit and connected with the signal input end;

a drain electrode of the first transistor is connected with a control electrode and a source electrode of the second transistor;

a drain electrode of the second transistor is the third end of the second sub-circuit and connected with the third end of the first sub-circuit; and

a high voltage signal or the second clock signal is inputted from the signal input end.