DETERMINATION CIRCUIT

• US 20170301397A1
• Filed: 06/28/2017
• Published: 10/19/2017
• Est. Priority Date: 09/11/2015
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Dozaka, Toshiaki
• Granted Patent: US 10,127,975 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A determination circuit of one embodiment includes first and second inverter circuits, a first transistor which turns on when receiving an asserted first signal, and a first capacity component including a first end which receives an inversion signal of the first signal. The second inverter circuit includes an input coupled to an output of the first inverter circuit, and includes an output coupled to an input of the first inverter circuit. The first node is coupled to a first potential node, the first transistor is coupled between the second node and a second potential node having a lower potential than a potential of the first potential node, and a second end of the first capacity component is coupled to the second node.

Claims

1. A determination circuit comprising:

a first inverter circuit;

a second inverter circuit which includes an input coupled to an output of the first inverter circuit and a first signal line, and includes an output coupled to an input of the first inverter circuit and a second signal line;

a first transistor which turns on when receiving an asserted first signal;

a first capacity component which has a first end which receives an inversion signal of the first signal;

a second transistor which has a gate coupled to a first bit line; and

a third transistor which has a gate coupled to a second bit line, wherein

a lower potential side node of the first inverter circuit is coupled to a first node through the second transistor, a lower potential side node of the second inverter circuit is coupled to the first node through the third transistor, the first transistor is coupled between the first node and a first potential node, and a second end of the first capacity component is coupled to the first node, or

a higher potential side node of the first inverter circuit is coupled to a second node through the second transistor, a higher potential side node of the second inverter circuit is coupled to the second node through the third transistor, the first transistor is coupled between the second node and a second potential node having a higher potential than a potential of the first potential node, and the second end of the first capacity component is coupled to the second node.

2. The circuit of claim 1, wherein:

the first signal is supplied to the first end of the first capacity component through odd logic inverters coupled in series.

3. The circuit of claim 1, wherein:

the first inverter circuit comprises a first resistance element or a p-type first MOSFET, and an n-type second MOSFET coupled in series to the first resistance element or the first MOSFET,

an end of the first resistance element or the first MOSFET opposite the second MOSFET is the higher potential side node of the first inverter circuit,

a source of the second MOSFET is the lower potential side node of the first inverter circuit,

the second inverter circuit comprises a second resistance element or a p-type third MOSFET, and an n-type fourth MOSFET coupled in series to the second resistance element or a third MOSFET,

an end of the second resistance element or the third MOSFET opposite the fourth MOSFET is the higher potential side node of the second inverter circuit, and

a source of the fourth MOSFET is the lower potential side node of the second inverter circuit.

4. The circuit of claim 1, wherein:

the first potential node receives a ground potential, and

the second potential node receives a power potential.

5. The circuit of claim 1, wherein:

at least one of the first inverter circuit and the second inverter circuit includes at least one transistor formed in a well, and

the determination circuit further comprises a second capacity component which has a first end coupled to the well and a second end which receives the first signal or an inversion signal of the first signal.

6. A determination circuit comprising:

a first inverter circuit;

a second inverter circuit which has a higher potential side node coupled to a higher potential node of the first inverter circuit at a first node, has a lower potential side node coupled to a lower potential side node of the first inverter circuit at a second node, includes an input coupled to an output of the first inverter circuit, a first bit line, and a first signal line, and includes an output coupled to an input of the first inverter circuit, a second bit line, and a second signal line;

a first transistor which is coupled between a first potential node and the first node or between the second node and a second potential node having a potential lower than a potential of the first potential node, and turns on when receiving an asserted first signal; and

a first capacity component, wherein

at least one of the first inverter circuit and the second inverter circuit includes at least one transistor disposed in a well, and

a first end of the first capacity component is coupled to the well, and

a second end of the first capacity component receives the first signal or an inversion signal of the first signal.

7. The circuit of claim 6, wherein

the first signal is coupled to the second end of the first capacity component through even logic inverters coupled in series.

8. The circuit of claim 6, wherein:

the first inverter circuit comprises a p-type first MOSFET and an n-type second MOSFET coupled to the first MOSFET in series,

a source of the first MOSFET is the higher potential side node of the first inverter circuit,

a source of the second MOSFET is the lower potential side node of the first inverter circuit,

the second inverter circuit comprises a p-type third MOSFET and an n-type fourth MOSFET coupled to the third MOSFET in series,

a source of the third MOSFET is the higher potential side node of the second inverter circuit,

a source of the fourth MOSFET is the lower potential side node of the second inverter circuit, and

the at least one transistor is one of the first to fourth MOSFETs.

9. The circuit of claim 8, wherein:

the determination circuit further comprises a second capacity component which has a first end coupled to a well in which the first and third MOSFETs are disposed, and a second end which receives an inversion signal of the first signal,

the second end of the first capacity component receives the first signal, and

the first end of the first capacity component is coupled to a well in which the second and fourth MOSFETs are disposed.

10. The circuit of claim 9, wherein:

the first signal is coupled to the second end of the first capacity component through even logic inverters coupled in series, and coupled to the second end of the second capacity component through odd logic inverters coupled in series.

11. The circuit of claim 6, wherein:

the first potential node receives a power potential, and

the second potential node receives a ground potential.