Multi-Bit-Per-Cell Three-Dimensional One-Time-Programmable Memory

• US 20170301405A1
• Filed: 04/14/2017
• Published: 10/19/2017
• Est. Priority Date: 04/14/2016
• Status: Active Grant

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC
• Inventors: ZHANG, Guobiao
• Granted Patent: US 10,102,917 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2013/0042 Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2216/12 Reading and writing aspects of erasable programmable read-only memories
• CPC Class Codes: G11C 29/78 using programmable devices
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

The present invention discloses a multi-bit-per-cell three-dimensional read-only memory (3D-OTP_MB). It comprises a plurality of OTP cells stacked above a semiconductor substrate. Each OTP cell comprises an antifuse layer, which is irreversibly switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed antifuses have different resistances.

Claims

1. A multi-bit-per-cell three-dimensional read-only memory (3D-OTP_MB), comprising:

a semiconductor substrate including transistors thereon;

a plurality of OTP cells stacked above said semiconductor substrate, each of said OTP cells comprising an antifuse layer, where said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming;

a plurality of contact vias coupling said OTP cells to said semiconductor substrate;

wherein said OTP cells have more than two states, the OTP cell in different states being programmed by different programming currents.

2. The 3D-OTP_MB according to claim 1, further comprising:

an OTP array comprising said plurality of OTP cells including a data OTP cell, a plurality of word lines including a data word line, and a plurality of bit lines including a data bit line;

an amplifier coupled with said data OTP cell through said data bit line.

3. The 3D-OTP_MB according to claim 2, wherein all OTP cells coupled with said data word line in said OTP array are read out during a read cycle.

4. The 3D-OTP_MB according to claim 3, wherein said word lines and said bit lines are charged to an input bias voltage of said amplifier during a pre-charge phase of said read cycle.

5. The 3D-OTP_MB according to claim 3, wherein a read voltage is applied to said data word line during a read phase of said read cycle.

6. The 3D-OTP_MB according to claim 2, wherein said OTP array further comprises:

a first dummy bit line associated with a first unprogrammed dummy OTP cell;

a second dummy bit line associated with a second programmed dummy OTP cell;

a first differential amplifier comprising a first input, wherein said first input is coupled with said first and second dummy bit lines.

7. The 3D-OTP_MB according to claim 6, wherein said OTP array further comprises:

a third dummy bit line associated with a third programmed dummy OTP cell, said second and third dummy OTP cells having a same state;

a fourth dummy bit line associated with a fourth programmed dummy OTP cell, said second and fourth dummy OTP cells having different states;

a second differential amplifier comprising a second input, wherein said second input is coupled with said third and fourth dummy bit lines.

8. The 3D-OTP_MB according to claim 2, wherein said OTP array further comprises:

a first dummy bit line associated with a first unprogrammed dummy OTP cell;

a second dummy bit line associated with a second programmed dummy OTP cell;

a third dummy bit line associated with a third programmed dummy OTP cell, said second and third dummy OTP cells having different states;

a differential amplifier comprising an input, wherein said input is coupled with said first and second dummy bit lines during a first measurement, and said input is coupled with said second and third dummy bit lines during a second measurement.

9. The 3D-OTP_MB according to claim 2, wherein said OTP array further comprises:

a dummy word line in parallel with said data word line;

a dummy bit line in parallel with said data bit line;

a first dummy OTP cell formed at the intersection of said dummy word line said dummy bit line, wherein said first OTP dummy cell is programmed;

a second dummy OTP cell formed at the intersection of said data word line and said dummy bit line, wherein said second dummy cell is unprogrammed.

10. The 3D-OTP_MB according to claim 1, further comprising a quasi-conductive layer, wherein the resistance of said antifuse layer is larger than the read resistance of said quasi-conductive layer.

19. The 3D-OTP_MB according to claim 2, wherein said OTP array further comprises:

a dummy word line in parallel with said data word line;

a dummy bit line in parallel with said data bit line;

a first dummy OTP cell formed at the intersection of said dummy word line said dummy bit line, said first dummy OTP cell is programmed;

a second dummy OTP cell formed at the intersection of said data word line and said dummy bit line, said second dummy OTP cell is unprogrammed.

20. The 3D-OTP_MB according to claim 1, further comprising a quasi-conductive layer, wherein the resistance of said antifuse layer is larger than the read resistance of said quasi-conductive layer.

11. A multi-bit-per-cell three-dimensional read-only memory (3D-OTP_MB), comprising:

a semiconductor substrate including transistors thereon;

a plurality of OTP cells stacked above said semiconductor substrate each of said OTP cells comprising an antifuse layer, where said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming;

a plurality of contact vias coupling said OTP cells to said semiconductor substrate;

wherein the resistance of said antifuse layer is determined by a programming current, said OTP cells being programmed by at least two programming currents.

12. The 3D-OTP_MB according to claim 11, further comprising:

an OTP array comprising said plurality of OTP cells including a data OTP cell, a plurality of word lines including a data word line, and a plurality of bit lines including a data bit line;

an amplifier coupled with said data OTP cell through said data bit line.

13. The 3D-OTP_MB according to claim 12, wherein all OTP cells coupled with said data word line in said OTP array are read out during a read cycle.

14. The 3D-OTP_MB according to claim 13, wherein said word lines and said bit lines are charged to an input bias voltage of said amplifier during a pre-charge phase of said read cycle.

15. The 3D-OTP_MB according to claim 13, wherein a read voltage is applied to said data word line during a read phase of said read cycle.

16. The 3D-OTP_MB according to claim 12, wherein said OTP array further comprises:

a first dummy bit line associated with a first unprogrammed dummy OTP cell;

a second dummy bit line associated with a second programmed dummy OTP cell;

a first differential amplifier comprising a first input, wherein said first input is coupled with said first and second dummy bit lines.

17. The 3D-OTP_MB according to claim 16, wherein said OTP array further comprises:

a third dummy bit line associated with a third programmed dummy OTP cell, said second and third dummy cells having a same state;

a fourth dummy bit line associated with a fourth programmed dummy OTP cell, said second and fourth dummy cells having different states;

a second differential amplifier comprising a second input, wherein said second input is coupled with said third and fourth dummy bit lines.

18. The 3D-OTP_MB according to claim 12, wherein said OTP array further comprises:

a first dummy bit line associated with a first unprogrammed dummy OTP cell;

a second dummy bit line associated with a second programmed dummy OTP cell;

a third dummy bit line associated with a third programmed dummy OTP cell, said second and third dummy OTP cells having different states;

a differential amplifier comprising an input, wherein said input is coupled with said first and second dummy bit lines during a first measurement, and said input is coupled with said second and third dummy bit lines during a second measurement.