METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES

• US 20170301577A1
• Filed: 05/30/2017
• Published: 10/19/2017
• Est. Priority Date: 11/25/2008
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: SANDERS, Paul W., JONES, Robert E., PETRAS, Michael F., RAMIAH, Chandrasekaram
• Granted Patent: US 9,837,299 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16503 comprising an intermetallic compound
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83365 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/58 : Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/162 : the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0296 : involving a specific disposition of the protective devices
• CPC Class Codes: H01L 27/0629 : in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/00 : Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01021 : Scandium [Sc]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
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• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates. An active device (AD) substrate has contacts on its upper portion. A ground plane is located between the AD substrate and an IPD substrate. The ground plane provides superior IPD to AD cross-talk attenuation.

Claims

1. A structure comprising circuitry for operation at one or more frequencies at least as high as a radio frequency, the circuitry comprising:

one or more active devices;

one or more passive devices electrically coupled to the one or more active devices; and

a ground plane separating the one or more active from the one or more passive devices;

wherein the structure comprises;

a first semiconductor substrate comprising at least part of the one or more active devices; and

a second semiconductor substrate overlying the first semiconductor substrate and supporting at least part of the one or more passive devices located over the second semiconductor substrate;

wherein the ground plane overlies the first semiconductor substrate and underlies at least part of the second semiconductor substrate;

wherein the circuitry further comprises one or more conductive paths passing through the second semiconductor substrate and electrically coupling the one or more passive devices to the one or more active devices.

2. The structure of claim 1 wherein the ground plane is formed in or on a bottom of the second semiconductor substrate.

3. The structure of claim 1 wherein the ground plane underlies all of the second semiconductor substrate.

4. The structure of claim 1 wherein the ground plane is part of an interconnect zone overlying the first semiconductor substrate and underlying at least part of the second semiconductor substrate.

5. The structure of claim 4 wherein the interconnect zone underlies all of the second semiconductor substrate.

6. The structure of claim 4 wherein the interconnect zone comprises a part of at least one said conductive path.

7. The structure of claim 1 wherein at least one said passive device comprises one or more inductor loops overlying the second semiconductor substrate.

8. The structure of claim 1 wherein the ground plane is configured to reduce eddy current losses at least at one of the one or more frequencies.

9. The structure of claim 1 wherein the second semiconductor substrate is a semiconductor material reducing electromagnetic coupling between the one or more passive devices and the one or more active devices at least at one of the one or more frequencies.

10. The structure of claim 1 wherein the second semiconductor substrate is a semiconductor material at least as effective as a silicon material having a resistivity of at least 1000 ohm-cm in reducing the electromagnetic coupling between the one or more passive devices and the one or more active devices at least at one of the one or more frequencies.

11. The structure of claim 1 wherein the second semiconductor substrate is a silicon material having a resistivity of at least 1000 ohm-cm.

12. A method comprising forming a structure comprising circuitry for operation at one or more frequencies at least as high as a radio frequency, the circuitry comprising:

one or more active devices;

one or more passive devices electrically coupled to the one or more active devices;

a ground plane separating the one or more active devices from the one or more passive devices; and

one or more conductive paths electrically coupling the one or more passive devices to the one or more active devices;

wherein forming the structure comprises;

providing a first semiconductor substrate comprising at least part of the one or more active devices;

providing a second semiconductor substrate supporting at least part of the one or more passive devices located over the second semiconductor substrate;

attaching together a plurality of components including the first and second semiconductor substrates, to form said structure, such that the ground plane overlies the first semiconductor substrate and underlies at least part of the second semiconductor substrate;

wherein the one or more conductive paths pass through the second semiconductor substrate to electrically couple the one or more passive devices to the one or more active devices.

13. The method of claim 12 wherein at least part of the ground plane is formed in or on a bottom of the second semiconductor substrate before said attaching.

14. The method of claim 12 wherein in said structure, the ground plane underlies all of the second semiconductor substrate.

15. The method of claim 12 wherein in said structure, the ground plane is part of an interconnect zone overlying the first semiconductor substrate and underlying at least part of the second semiconductor substrate.

15-1. The method of claim 15 wherein the interconnect zone underlies all of the second semiconductor substrate.

16. The method of claim 15 wherein the interconnect zone comprises a part of at least one said conductive path.

17. The method of claim 12 wherein at least one said passive device comprises one or more inductor loops overlying the second semiconductor substrate.

18. The method of claim 12 wherein the ground plane is configured to reduce eddy current losses at least at one of the one or more frequencies.

19. The method of claim 12 wherein the second semiconductor substrate is a semiconductor material reducing electromagnetic coupling between the one or more passive devices and the one or more active devices at least at one of the one or more frequencies.

20. The method of claim 19 wherein the semiconductor material of the second semiconductor substrate is a silicon material having a resistivity of at least 1000 ohm-cm.