3DIC Formation with Dies Bonded to Formed RDLs

• US 20170301650A1
• Filed: 04/15/2016
• Published: 10/19/2017
• Est. Priority Date: 04/15/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Yeh, Sung-Feng, Chen, Ming-Fa
• Granted Patent: US 10,026,716 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02373 Layout of the redistribution layers
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04 Structure, shape, material or disposition of the bonding areas prior to the connecting process
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05576 : being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/05624 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05687 : Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05688
• CPC Class Codes: H01L 2224/0569 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/08 : of an individual bonding area
• CPC Class Codes: H01L 2224/08145 : the bodies being stacked
• CPC Class Codes: H01L 2224/08225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/08237 : the bonding area connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/21 : of an individual HDI interconnect
• CPC Class Codes: H01L 2224/2518 : being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/73251 : on different surfaces
• CPC Class Codes: H01L 2224/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80006 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/80204 : with a graded temperature profile
• CPC Class Codes: H01L 2224/80424 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/80447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/80484 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80907 : Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
• CPC Class Codes: H01L 2224/80948 : Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82101 : by additive methods, e.g. direct writing
• CPC Class Codes: H01L 2224/82106 : by subtractive methods
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9222 : Sequential connecting processes
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 23/295 : containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/89 : using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/20106 : Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K
• CPC Class Codes: H01L 2924/20107 : Temperature range 250 C=<T<300 C, 523.15K =<T< 573.15K
• CPC Class Codes: H01L 2924/20108 : Temperature range 300 C=<T<350 C, 573.15K =<T< 623.15K
• CPC Class Codes: H01L 2924/20109 : Temperature range 350 C=<T<400 C, 623.15K =<T< 673.15K
• CPC Class Codes: H01L 2924/2011 : Temperature range 400 C=<T<450 C, 673.15K =<T< 723.15K

Abstract

A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.

Claims

1. A method comprising:

forming a first dielectric layer over a carrier;

forming a first plurality of bond pads in the first dielectric layer;

performing a first planarization to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other;

bonding a first device die to the first dielectric layer and portions of the first plurality of bond pads through hybrid bonding;

encapsulating the first device die in a first encapsulating material; and

demounting the carrier from the first device die and the first dielectric layer.

2. The method of claim 1 further comprising forming a through-via starting from one of the first plurality of bond pads, wherein the through-via is encapsulated in the first encapsulating material.

3. The method of claim 2, wherein the through-via is plated on the one of the first plurality of bond pads before the encapsulating, and during the first planarization, the through-via is planarized.

4. The method of claim 2, wherein the forming the through-via comprises:

removing portions of the first encapsulating material to expose the one of the first plurality of bond pads; and

plating the through-via.

5. The method of claim 4 further comprising, after the plating the through-via, performing a second planarization on the first encapsulating material.

6. The method of claim 1 further comprising:

forming a second dielectric layer over the first device die and the first encapsulating material;

forming a second plurality of bond pads in the second dielectric layer;

performing a second planarization to level top surfaces of the second dielectric layer and the second plurality of bond pads with each other;

bonding a second device die to the second dielectric layer and portions of the second plurality of bond pads through hybrid bonding; and

encapsulating the second device die in a second encapsulating material.

7. The method of claim 1 further comprising:

removing portions of the first encapsulating material to expose an additional one of the first plurality of bond pads; and

forming a solder region joined to the additional one of the first plurality of bond pads.

8. The method of claim 1, wherein the encapsulating the first encapsulating material comprises depositing a dielectric material formed of silicon oxide, silicon nitride, or silicon oxynitride.

9. The method of claim 1 further comprising, after the carrier is demounted, forming a plurality of solder regions electrically coupling to the first plurality of bond pads, wherein the plurality of solder regions is on an opposite side of the first dielectric layer than the first device die.

10. A method comprising:

forming a first dielectric layer over a carrier;

forming a plurality of redistribution lines over the first dielectric layer;

forming a second dielectric layer over the plurality of redistribution lines;

forming a plurality of bond pads in the second dielectric layer, with top surfaces of the plurality of bond pads substantially coplanar with a top surface of the second dielectric layer;

bonding a device die, wherein a surface dielectric layer of the device die is bonded to the second dielectric layer, and metal pads in the device die are bonded to the plurality of bond pads through metal-to-metal bonding;

encapsulating the device die in an encapsulating material;

demounting the carrier to reveal the first dielectric layer; and

forming electrical connections penetrating through the first dielectric layer to electrically couple to the plurality of redistribution lines.

11. The method of claim 10 further comprising plating a through-via starting from one of the plurality of bond pads, wherein the plating is performed without using a seed layer.

12. The method of claim 11, wherein the through-via is plated on the one of the plurality of bond pads before the encapsulating.

13. The method of claim 11, wherein the forming the through-via comprises:

removing a portion of the encapsulating material to expose the one of the plurality of bond pads; and

plating the through-via from the one of the plurality of bond pads.

14. The method of claim 11 further comprising:

removing a portion of the encapsulating material to expose an additional one of the plurality of bond pads; and

forming a solder region joined to the additional one of the plurality of bond pads.

15. The method of claim 11, wherein the encapsulating the encapsulating material comprises depositing a dielectric material formed of silicon oxide, silicon nitride, or silicon oxynitride.

16-20. -20. (canceled)

21. A method comprising:

forming a dielectric layer over a glass carrier;

forming a plurality of bond pads in the dielectric layer through dual damascene;

bonding a device die to the dielectric layer and portions of the plurality of bond pads through hybrid bonding, wherein a surface dielectric layer of the device die is bonded to the dielectric layer, and metal pads in the device die are bonded to the plurality of bond pads through metal-to-metal bonding;

encapsulating the device die in an encapsulating material;

etching the encapsulating material to expose one of the plurality of bond pads;

plating a through-via from the one of the plurality of bond pads; and

demounting the glass carrier from the device die and the dielectric layer.

22. The method of claim 21, wherein the encapsulating material comprises silicon oxide, silicon nitride, or silicon oxynitride.

23. The method of claim 21 further comprising planarizing the encapsulating material.

24. The method of claim 21 further comprising forming redistribution lines over the encapsulating material, wherein one of the redistribution lines is electrically coupled to the through-via.

25. The method of claim 21 further comprising, after the glass carrier is demounted, forming conductive features penetrating through the dielectric layer.