METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

• US 20170301731A1
• Filed: 07/06/2017
• Published: 10/19/2017
• Est. Priority Date: 02/24/2014
• Status: Active Grant

• Current Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Original Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Inventors: MASUOKA, Fujio, NAKAMURA, Hiroki
• Granted Patent: US 9,954,032 B2
• Time in Patent Office: Days
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/046 by diffusion, e.g. photo-dissolution
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/861 Thermal details
• CPC Class Codes: H10N 70/8613 Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A method for producing a memory device and semiconductor device includes forming pillar-shaped phase change layers and lower electrodes in two or more rows and two or more columns on a semiconductor substrate. A reset gate insulating film is formed that surrounds the pillar-shaped phase change layers and the lower electrodes, and a reset gate is formed that surrounds the pillar-shaped phase change layers that function as memory devices arranged in two or more rows and two or more columns.

Claims

1. A method for producing a memory device, the method comprising:

a sixth step of forming pillar-shaped phase change layers and lower electrodes arranged in two or more rows and two or more columns on a semiconductor substrate, forming a reset gate insulating film that surrounds the pillar-shaped phase change layers and the lower electrodes, and forming a reset gate that surrounds the pillar-shaped phase change layers that function as memory devices arranged in two or more rows and two or more columns.

2. A method for producing a semiconductor device, the method comprising:

a first step of forming fin-shaped semiconductor layers on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layers;

a second step following the first step, the second step including forming a second insulating film around the fin-shaped semiconductor layers, depositing and planarizing a first polysilicon on the second insulating film, forming a second resist for forming gate lines, first pillar-shaped semiconductor layers, second pillar-shaped semiconductor layers, and a contact line so that the second resist extends in a direction perpendicular to a direction in which the fin-shaped semiconductor layers extend, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layers so as to form first pillar-shaped semiconductor layers, first dummy gates formed of the first polysilicon, second pillar-shaped semiconductor layers, and second dummy gates formed of the first polysilicon;

a third step following the second step, the third step including forming a fourth insulating film around the first pillar-shaped semiconductor layers, the second pillar-shaped semiconductor layers, the first dummy gates, and the second dummy gates, depositing a second polysilicon around the fourth insulating film, and etching the second polysilicon so as to allow the second polysilicon to remain on side walls of the first dummy gates, the first pillar-shaped semiconductor layers, the second dummy gates, and the second pillar-shaped semiconductor layers so as to form third dummy gates and fourth dummy gates;

a fourth step of forming second diffusion layers in upper portions of the fin-shaped semiconductor layers, lower portions of the first pillar-shaped semiconductor layers, and lower portions of the second pillar-shaped semiconductor layers, forming a fifth insulating film around the third dummy gates and the fourth dummy gates, etching the fifth insulating film into a side wall shape so as to form side walls formed of the fifth insulating film, and forming a metal-semiconductor compound on the second diffusion layers;

a fifth step following the fourth step, the fifth step including depositing and planarizing an interlayer insulating film, exposing upper portions of the first dummy gates, the second dummy gates, the third dummy gates, and the fourth dummy gates, removing the first dummy gates, the second dummy gates, the third dummy gates, and the fourth dummy gates, removing the second insulating film and the fourth insulating film, forming a gate insulating film around the first pillar-shaped semiconductor layers, around the second pillar-shaped semiconductor layers, and on an inner side of the fifth insulating film, forming a fourth resist for removing the gate insulating film around bottom portions of the second pillar-shaped semiconductor layers, removing the gate insulating film around the bottom portions of the second pillar-shaped semiconductor layers, depositing a metal, and etching back the metal so as to form gate electrodes and gate lines around the first pillar-shaped semiconductor layers and form contact electrodes and a contact line around the second pillar-shaped semiconductor layers; and

a sixth step following the fifth step, the sixth step including depositing and planarizing a second interlayer insulating film to expose upper portions of the first pillar-shaped semiconductor layers, forming pillar-shaped phase change layers and lower electrodes on the exposed first pillar-shaped semiconductor layers, forming a reset gate insulating film that surrounds the pillar-shaped phase change layers and the lower electrodes, and forming a reset gate that surrounds the pillar-shaped phase change layers that function as memory devices.

3. The method for producing a semiconductor device according to claim 2, further comprising forming a third insulating film on the first polysilicon after the first polysilicon is deposited and planarized on the second insulating film.

4. The method for producing a semiconductor device according to claim 2, wherein after the fourth insulating film is formed around the first pillar-shaped semiconductor layers, the first dummy gates, the second pillar-shaped semiconductor layers, and the second dummy gates, a third resist is formed and etched back to expose upper portions of the first pillar-shaped semiconductor layers and first diffusion layers are formed in the upper portions of the first pillar-shaped semiconductor layers.