SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND REPLACEMENT METAL GATE STRUCTURE AND RELATED METHODS
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Abstract
A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.
27 Citations
31 Claims
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1-9. -9. (canceled)
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10. A semiconductor device comprising:
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a substrate having a channel recess therein; a plurality of spaced apart shallow trench isolation (STI) regions in said substrate; source and drain regions spaced apart in the substrate and between a pair of the STI regions; and a superlattice channel in the channel recess of said substrate and extending between the source and drain regions, the superlattice channel contacting the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and a replacement gate over the superlattice channel. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A semiconductor device comprising:
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a substrate having a channel recess therein; a plurality of spaced apart shallow trench isolation (STI) regions in said substrate; source and drain regions spaced apart in the substrate and between a pair of the STI regions; a superlattice channel in the channel recess of said substrate and extending between the source and drain regions, the superlattice channel contacting the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; and a replacement gate comprising a high K dielectric layer over the superlattice channel and a metal gate electrode over the high K dielectric layer. - View Dependent Claims (20, 21, 22)
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23. A semiconductor device comprising:
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a substrate; a pair of spaced apart isolation regions in said substrate; source and drain regions spaced apart in the substrate and between the pair of the isolation regions; the substrate having a channel recess extending between the source and drain regions; a superlattice channel in the channel recess and contacting the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and a gate over the superlattice channel comprising a dielectric layer and a metal gate electrode thereon. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31)
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Specification