OVERFLOW DETECTION AND CORRECTION IN STATE MACHINE ENGINES

• US 20170308385A1
• Filed: 07/10/2017
• Published: 10/26/2017
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Brown, Brian Lewis
• Granted Patent: US 11,016,790 B2
• Time in Patent Office: Days
• CPC Class Codes: G05B 11/01 electric
• CPC Class Codes: G05B 19/045 using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 7/00 Methods or arrangements for processing data by operating upon the order or content of the data handled logic circuits H03K19/00
• CPC Class Codes: G06F 9/4498 Finite state machines

Abstract

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

Claims

1. A device, comprising:

a core configured to analyze data;

a storage location configured to store the data to be transmitted to the core; and

a bus control system configured to receive an indication of an amount of data locations being utilized in the storage location and transmit a halt signal configured to halt a write operation based, at least in part, on the amount of data locations being utilized in the storage location.

2. The device of claim 1, wherein the bus control system is configured to compare the indication with a threshold.

3. The device of claim 2, wherein the bus control system is configured to generate the halt signal as indicative of an overflow condition based, at least in part, on whether the indication meets or exceeds the threshold.

4. The device of claim 2, wherein the bus control system is configured to determine if any of the data locations are available in the storage location based, at least in part, on whether the indication meets or exceeds the threshold.

5. The device of claim 4, wherein the bus control system is configured to transmit an indication to allow writing of data to the determined available data locations.

6. The device of claim 1, wherein the bus control system is configured to monitor a transmission of the data from the storage location.

7. The device of claim 6, wherein the bus control system is configured to transmit a restart signal based, at least in part, on a status of the transmission of the data from the storage location.

8. The device of claim 6, wherein the bus control system is configured to transmit a restart signal if the transmission of the data from the storage location is complete.

9. The device of claim 8, wherein the device initializes a second write operation based, at least in part, on the restart signal.

10. The device of claim 1, wherein the storage location comprises a buffer.

11. The device of claim 10, wherein the buffer comprises a data buffer.

12. The device of claim 10, wherein the buffer comprises a process buffer.

13. The device of claim 1, wherein the storage location comprises a register.

14. A system, comprising:

a data analysis engine comprising a core;

a processor coupled to the data analysis engine, wherein the processor is configured to transmit instructions corresponding to input data to be analyzed via the data analysis engine;

a memory coupled to the data analysis engine, wherein the state machine engine is configured to receive the input data to be analyzed from the memory, wherein the data analysis engine comprises;

a bus control system configured to halt a write operation of data to the core, wherein the core comprises a plurality of configurable elements and each of the plurality of configurable elements comprises a plurality of memory cells configured to analyze the data and to output a result of the analysis; and

a storage location configured to store the data, wherein the bus control system is configured to halt the write operation based, at least in part, on an indication of an amount of data locations being utilized in the storage location.

15. The system of claim 14, wherein the bus control system is configured to determine if any of the data locations are available in the storage location and transmit an indication to allow writing of additional data to the available data locations prior to halting the write operation.

16. The system of claim 14, wherein the storage location comprises a buffer.

17. The system of claim 14, wherein the storage location comprises a register.

18. The system of claim 14, wherein the bus control system is configured to monitor a transmission of the data from the storage location.

19. A device, comprising a bus control system configured to halt a write operation of data from a buffer interface to a core, wherein the core comprises a plurality of configurable elements and each of the plurality of configurable elements comprises a plurality of memory cells configured to analyze the data and to output a result of the analysis.

20. The device of claim 19, wherein the bus control system is configured to halt the write operation based upon detection of an overflow condition at a storage location configured to store the data prior to analysis.