EVENT-DRIVEN UNIVERSAL NEURAL NETWORK CIRCUIT
First Claim
1. A method comprising:
- for a port of a neural module comprising a plurality of neurons and a plurality of ports;
classifying the port into one of a plurality of port types, wherein the port is classified into a different port type that another port of the plurality of ports;
interconnecting the port to at least one synapse classified into the same port type as the port;
maintaining synaptic connectivity information indicative of the at least one synapse, a total sum of synaptic weights of the at least one synapse, and a target sum; and
selectively updating a set of learning rules for the at least one synapse based on the total sum and the target sum.
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Abstract
The present invention provides an event-driven universal neural network circuit. The circuit comprises a plurality of neural modules. Each neural module comprises multiple digital neurons such that each neuron in a neural module has a corresponding neuron in another neural module. An interconnection network comprising a plurality of digital synapses interconnects the neural modules. Each synapse interconnects a first neural module to a second neural module by interconnecting a neuron in the first neural module to a corresponding neuron in the second neural module. Corresponding neurons in the first neural module and the second neural module communicate via the synapses. Each synapse comprises a learning rule associating a neuron in the first neural module with a corresponding neuron in the second neural module. A control module generates signals which define a set of time steps for event-driven operation of the neurons and event communication via the interconnection network.
6 Citations
15 Claims
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1. A method comprising:
for a port of a neural module comprising a plurality of neurons and a plurality of ports; classifying the port into one of a plurality of port types, wherein the port is classified into a different port type that another port of the plurality of ports; interconnecting the port to at least one synapse classified into the same port type as the port; maintaining synaptic connectivity information indicative of the at least one synapse, a total sum of synaptic weights of the at least one synapse, and a target sum; and selectively updating a set of learning rules for the at least one synapse based on the total sum and the target sum. - View Dependent Claims (2, 3, 4, 5)
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6. A system comprising a computer processor, a computer-readable hardware storage medium, and program code embodied with the computer-readable hardware storage medium for execution by the computer processor to implement a method comprising:
for a port of a neural module comprising a plurality of neurons and a plurality of ports; classifying the port into one of a plurality of port types, wherein the port is classified into a different port type that another port of the plurality of ports; interconnecting the port to at least one synapse classified into the same port type as the port; maintaining synaptic connectivity information indicative of the at least one synapse, a total sum of synaptic weights of the at least one synapse, and a target sum; and selectively updating a set of learning rules for the at least one synapse based on the total sum and the target sum. - View Dependent Claims (7, 8, 9, 10)
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11. A computer program product comprising a computer-readable hardware storage medium having program code embodied therewith, the program code being executable by a computer to implement a method comprising:
for a port of a neural module comprising a plurality of neurons and a plurality of ports; classifying the port into one of a plurality of port types, wherein the port is classified into a different port type that another port of the plurality of ports; interconnecting the port to at least one synapse classified into the same port type as the port; maintaining synaptic connectivity information indicative of the at least one synapse, a total sum of synaptic weights of the at least one synapse, and a target sum; and selectively updating a set of learning rules for the at least one synapse based on the total sum and the target sum. - View Dependent Claims (12, 13, 14, 15)
Specification