MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

• US 20170309550A1
• Filed: 03/19/2017
• Published: 10/26/2017
• Est. Priority Date: 04/22/2016
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: DANNO, Tadatoshi, MATSUSHITA, Tsukasa, NISHIKIZAWA, Atsushi
• Granted Patent: US 9,837,339 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4828 Etching etching for cleaning without patterning H01L21/4835
• CPC Class Codes: H01L 21/485 Adaptation of interconnections, e.g. engineering charges, repair techniques
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49173 Radial fan-out arrangements
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/85203 : Thermocompression bonding
• CPC Class Codes: H01L 2224/85207 : Thermosonic bonding
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/293 : Organic, e.g. plastic
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49503 : characterised by the die pad
• CPC Class Codes: H01L 23/4952 : the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49551 : characterised by bent parts
• CPC Class Codes: H01L 23/49582 : Metallic layers on lead frames
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/43 : Manufacturing methods
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/46 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

An improvement is achieved in the reliability of a semiconductor device. After a resin sealing portion is formed to seal a die pad, a semiconductor chip mounted over the die pad, a plurality of leads, and a plurality of wires electrically connecting a plurality of pad electrodes of the semiconductor chip with the leads, the resin sealing portion and the leads are cut with a rotary blade to manufacture the semiconductor device. In the semiconductor device, at least a portion of each of first and second leads is exposed from a lower surface of the sealing portion. End surfaces of the first and second leads as the respective cut surfaces thereof are exposed from each of side surfaces of the sealing portion as the cut surfaces of the resin sealing portion. The distance between a lower side of the end surface of the first lead and an upper surface of the sealing portion is smaller than the distance between an upper side of the end surface of the second lead adjacent thereto and the upper surface of the sealing portion.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

(a) providing a lead frame having a chip mounting portion and a plurality of leads;

(b) mounting a semiconductor chip over the chip mounting portion, the semiconductor chip having a plurality of pad electrodes;

(c) after the step (b), electrically connecting the plurality of pad electrodes of the semiconductor chip with the plurality of leads via a plurality of wires, respectively;

(d) after the step (c), forming a resin sealing portion which seals the semiconductor chip, the plurality of wires, the chip mounting portion and the plurality of leads; and

(e) after the step (d), cutting the resin sealing portion and the plurality of leads with a rotary blade, wherein the resin sealing portion formed in the step

(d) has a first upper surface and a first lower surface which are located opposite to each other,

wherein, in the step (d), at least a part of each of the plurality of leads is exposed from the first lower surface of the resin sealing portion,

wherein, in the step (e), a cut surface of each of the plurality of leads resulting from the step (e) is exposed from a cut surface of the resin sealing portion resulting from the step (e),

wherein the plurality of leads include a first lead and a second lead located next to the first lead,

wherein a first end surface as the cut surface of the first lead resulting from the step (e) has a first upper side closer to the first upper surface and a first lower side far away from the first upper surface,

wherein a second end surface as the cut surface of the second lead resulting from the step (e) has a second upper side closer to the first upper surface and a second lower side far away from the first upper surface, and

wherein a distance between the first lower side and the first upper surface in a thickness direction of the resin sealing portion is smaller than a distance between the second upper side and the first upper surface in the thickness direction of the resin sealing portion.

2. The method of manufacturing the semiconductor device according to claim 1,

wherein, in the step (d), the plurality of wires are individually connected with the plurality of leads while an ultrasonic wave is applied thereto.

3. The method of manufacturing the semiconductor device according to claim 2,

wherein each of the plurality of wires is a copper wire.

4. The method of manufacturing the semiconductor device according to claim 1,

wherein a first dimension of the first end surface in the thickness direction of the resin sealing portion is larger than a second dimension of the second end surface in the thickness direction of the resin sealing portion.

5. The method of manufacturing the semiconductor device according to claim 1,

wherein, in the step (a), the lead frame is produced by etching.

6. The method of manufacturing the semiconductor device according to claim 1,

wherein the plurality of leads are disposed so as to surround the chip mounting portion,

wherein the plurality of leads include a plurality of the first leads and a plurality of the second leads, and

wherein the first leads and the second leads are alternately disposed.

7. The method of manufacturing the semiconductor device according to claim 1,

wherein a third dimension of the first end surface in a direction parallel with the first lower surface is smaller than a fourth dimension of the second end surface in the direction parallel with the first lower surface.

8. The method of manufacturing the semiconductor device according to claim 1,

wherein the first lead integrally has a first thicker portion and a first thinner portion thinner than the first thicker portion which are next to each other in an extending direction of the first lead,

wherein the first thicker portion is located closer to the chip mounting portion than the first thinner portion,

wherein, in the step (d), a second lower surface of the first thicker portion is exposed from the first lower surface of the resin sealing portion, while a third lower surface of the first thinner portion is covered with the resin sealing portion,

wherein the first end surface is a cut surface of the first thinner portion resulting from the step (e),

wherein the second lead integrally has a second thicker portion and a second thinner portion thinner than the second thicker portion which are next to each other in an extending direction of the second lead,

wherein the second thicker portion is located closer to the chip mounting portion than the second thinner portion, and

wherein the second end surface is a cut surface of the second thinner portion resulting from the step (e).

9. The method of manufacturing the semiconductor device according to claim 8,

wherein a first width of the first thinner portion is smaller than a second width of the first thicker portion.

10. The method of manufacturing the semiconductor device according to claim 9,

wherein a third width of the second thinner portion is smaller than a fourth width of the second thicker portion.

11. A method of manufacturing a semiconductor device, comprising the steps of:

(a) providing a lead frame having a first device formation region and a second device formation region located next to the first device formation region via a dam bar,

wherein each of the first and second device formation regions has a chip mounting portion, a plurality of suspension leads supporting the chip mounting portion, and a plurality of leads;

(b) mounting a first semiconductor chip over the chip mounting portion in the first device formation region and mounting a second semiconductor chip over the chip mounting portion in the second device formation region,

wherein each of the first and second semiconductor chips having a plurality of pad electrodes;

(c) after the step (b), electrically connecting the plurality of pad electrodes of the first semiconductor chip with the plurality of leads in the first device formation region via a plurality of first wires, respectively, and electrically connecting the plurality of pad electrodes of the second semiconductor chip with the plurality of leads in the second device formation region via a plurality of second wires, respectively; and

(d) after the step (c), forming a resin sealing portion so as to cover the first and second device formation regions of the lead frame,

wherein the resin sealing portion seals the first semiconductor chip, the plurality of first wires, the chip mounting portion, and the plurality of leads in the first device formation region, and the second semiconductor chip, the plurality of second wires, the chip mounting portion, and the plurality of leads in the second device formation region,

wherein the resin sealing portion has a first upper surface and a first lower surface which are located opposite to each other, and

wherein at least a portion of each of the plurality of leads in the first and second device formation regions is exposed from the first lower surface of the resin sealing portion;

(e) after the step (d), cutting the resin sealing portion, the plurality of leads, the plurality of suspension leads, and the dam bar between the first and second device formation regions with a rotary blade,

wherein a cut surface of each of the plurality of leads resulting from the step (e) is exposed from a cut surface of the resin sealing portion resulting from the step (e),

wherein the plurality of leads include a first lead and a second lead located next to the first lead,

wherein a first end surface as the cut surface of the first lead resulting from the step (e) has a first upper side closer to the first upper surface and a first lower side far away from the first upper surface,

wherein a second end surface as the cut surface of the second lead resulting from the step (e) has a second upper side closer to the first upper surface and a second lower side far away from the first upper surface, and

wherein a distance between the first lower side and the first upper surface in a thickness direction of the resin sealing portion is smaller than a distance between the second upper side and the first upper surface in the thickness direction of the resin sealing portion.

12. The method of manufacturing the semiconductor device according to claim 11,

wherein the first lead integrally has a first thicker portion and a first thinner portion thinner than the first thicker portion which are next to each other in an extending direction of the first lead,

wherein the first thicker portion is located closer to the chip mounting portion than the first thinner portion, while the first thinner portion is connected with the dam bar,

wherein the second lead integrally has a second thicker portion and a second thinner portion thinner than the second thicker portion which are next to each other in an extending direction of the second lead,

wherein the second thicker portion is located closer to the chip mounting portion than the second thinner portion, while the second thinner portion is connected with the dam bar,

wherein the first end surface is a cut surface of the first thinner portion resulting from the step (e),

wherein the second end surface is a cut surface of the second thinner portion resulting from the step (e),

wherein a first portion of the dam bar which is connected with the first thinner portion of the first lead has the same thickness as that of the first thinner portion of the first lead, and

wherein a second portion of the dam bar which is connected with the second thinner portion of the second lead has the same thickness as that of the second thinner portion of the second lead.

13. A semiconductor device, comprising:

a chip mounting portion;

a semiconductor chip mounted over the chip mounting portion and having a plurality of pad electrodes;

a plurality of leads;

a plurality of wires electrically connecting the plurality of pad electrodes of the semiconductor chip with the plurality of leads; and

a resin sealing portion which seals the chip mounting portion, the semiconductor chip, the wires, and the leads,

wherein the resin sealing portion has a first upper surface and a first lower surface which are located opposite to each other, and a plurality of side surfaces located between the first upper surface and the first lower surface,

wherein at least a portion of each of the plurality of leads is exposed from the first lower surface of the resin sealing portion,

wherein the plurality of leads include a first lead and a second lead located next to the first lead,

wherein a first end surface of the first lead and a second end surface of the second lead are exposed from a first side surface which is among the side surfaces of the resin sealing portion,

wherein the first end surface of the first lead has a first upper side closer to the first upper surface and a first lower side far away from the first upper surface,

wherein the second end surface of the second lead has a second upper side closer to the first upper surface and a second lower side far away from the first upper surface,

wherein, on the first end surface of the first lead and the second end surface of the second lead, metal burrs are formed to extend in respective directions parallel with each of the first lower surface and the first side surface, and

wherein a distance between the first lower side and the first upper surface in a thickness direction of the resin sealing portion is smaller than a distance between the second upper side and the first upper surface in the thickness direction of the resin sealing portion.

14. The semiconductor device according to claim 13,

wherein a first dimension of the first end surface in the thickness direction of the resin sealing portion is larger than a second dimension of the second end surface in the thickness direction of the resin sealing portion.

15. The semiconductor device according to claim 13,

wherein the plurality of leads are disposed so as to surround the chip mounting portion,

wherein the plurality of leads include a plurality of the first leads and a plurality of the second leads, and

wherein the first leads and the second leads are alternately disposed.

16. The semiconductor device according to claim 13,

wherein the first lead integrally has a first thicker portion and a first thinner portion thinner than the first thicker portion which are next to each other in an extending direction of the first lead,

wherein the first thicker portion is located closer to the chip mounting portion than the first thinner portion,

wherein a second lower surface of the first thicker portion is exposed from a first lower surface of the resin sealing portion, while a third lower surface of the first thinner portion is covered with the resin sealing portion,

wherein the first end surface is formed of the first thinner portion,

wherein the second lead integrally has a second thicker portion and a second thinner portion thinner than the second thicker portion which are next to each other in an extending direction of the second lead,

wherein the second thicker portion is located closer to the chip mounting portion than the second thinner portion, and

wherein the second end surface is formed of the second thinner portion.

17. The semiconductor device according to claim 16

wherein a fourth lower surface of the second thicker portion and a fifth lower surface of the second thinner portion are exposed from the first lower surface of the resin sealing portion.

18. The semiconductor device according to claim 16,

wherein a first width of the first thinner portion is smaller than a second width of the first thicker portion.

19. The semiconductor device according to claim 18,

wherein a third width of the second thinner portion is smaller than a fourth width of the second thicker portion.

20. The semiconductor device according to claim 13,

wherein a third dimension of the first end surface in a direction parallel with the first lower surface is smaller than a fourth dimension of the second end surface in the direction parallel with the first lower surface.