Engineered Substrate Including Light Emitting Diode and Power Circuitry

• US 20170309676A1
• Filed: 04/19/2017
• Published: 10/26/2017
• Est. Priority Date: 04/22/2016
• Status: Active Application

• Current Assignee: Qromis, Inc.
• Original Assignee: Quora Technology, Inc.
• Inventors: Odnoblyudov, Vladimir, Risbud, Dilip, Basceri, Cem
• Granted Patent: US 10,290,674 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A gallium nitride based integrated circuit architecture includes a first electronic device including a first set of III-N epitaxial layers and a second electronic device including a second set of III-N epitaxial layers. The gallium nitride based integrated circuit architecture also includes one or more interconnects between the first electronic device and the second electronic device. The first electronic device and the second electronic device are disposed in a chip scale package.

Claims

1. A gallium nitride based integrated circuit architecture comprising:

a first electronic device including a first set of III-N epitaxial layers;

a second electronic device including a second set of III-N epitaxial layers; and

one or more interconnects between the first electronic device and the second electronic device, wherein the first electronic device and the second electronic device are disposed in a chip scale package.

2. The gallium nitride based integrated circuit architecture of claim 1 wherein the first electronic device comprises a high electron mobility transistor (HEMT).

3. The gallium nitride based integrated circuit architecture of claim 1 wherein the second electronic device comprises a light emitting diode (LED).

4. The gallium nitride based integrated circuit architecture of claim 1 wherein:

the first electronic device comprises a high electron mobility transistor (HEMT) including a source, a gate, and a drain;

the second electronic device comprises a light emitting diode (LED) including an anode and a cathode, and

the drain of the HEMT is connected to the anode of the LED.

5. The gallium nitride based integrated circuit architecture of claim 1 wherein the second set of III-N epitaxial layers are disposed on the first set of III-N epitaxial layers.

6. The gallium nitride based integrated circuit architecture of claim 1 further comprising an encapsulation layer disposed adjacent the first electronic device.

7. A method of fabricating a III-nitride integrated circuit, the method comprising:

providing a engineered substrate;

joining a single crystal layer to the engineered substrate;

growing a first set of III-N epitaxial layers coupled to the single crystal layer;

growing a second set of III-N epitaxial layers coupled to the first set of III-N epitaxial layers;

forming a first electronic device disposed at least partially in the first set of III-N epitaxial layers;

forming a second electronic device disposed at least partially in the second set of III-N epitaxial layers;

forming one or more interconnects between the first electronic device and the second electronic device; and

encapsulating the first electronic device, the second electronic device, and the one or more interconnects in a chip scale package.

8. The method of claim 7 wherein the first set of III-N epitaxial layers comprise GaN and the second set of III-N epitaxial layers comprise GaN.

9. The method of claim 7 wherein providing an engineered substrate comprises:

providing a polycrystalline ceramic core;

encapsulating the polycrystalline ceramic core in a first tetraethyl orthosilicate (TEOS) layer;

encapsulating the first TEOS layer in a polysilicon layer;

encapsulating the polysilicon layer in a second TEOS layer; and

encapsulating the second TEOS layer in a silicon nitride layer.

10. The method of claim 7 further comprising forming one or more isolating III-N epitaxial layers disposed between the first set of III-N epitaxial layers and the second set of III-N epitaxial layers.

11. The method of claim 7 further comprising forming one or more buffer layers between the single crystal layer and the first set of III-N epitaxial layers.

12. The method of claim 7 further comprising forming an emission structure including a transparent material and a phosphor, wherein the emission structure is adjacent the first electronic device and the second electronic device.