Engineered Substrate Including Light Emitting Diode and Power Circuitry
First Claim
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1. A gallium nitride based integrated circuit architecture comprising:
- a first electronic device including a first set of III-N epitaxial layers;
a second electronic device including a second set of III-N epitaxial layers; and
one or more interconnects between the first electronic device and the second electronic device, wherein the first electronic device and the second electronic device are disposed in a chip scale package.
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Abstract
A gallium nitride based integrated circuit architecture includes a first electronic device including a first set of III-N epitaxial layers and a second electronic device including a second set of III-N epitaxial layers. The gallium nitride based integrated circuit architecture also includes one or more interconnects between the first electronic device and the second electronic device. The first electronic device and the second electronic device are disposed in a chip scale package.
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Citations
12 Claims
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1. A gallium nitride based integrated circuit architecture comprising:
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a first electronic device including a first set of III-N epitaxial layers; a second electronic device including a second set of III-N epitaxial layers; and one or more interconnects between the first electronic device and the second electronic device, wherein the first electronic device and the second electronic device are disposed in a chip scale package. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of fabricating a III-nitride integrated circuit, the method comprising:
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providing a engineered substrate; joining a single crystal layer to the engineered substrate; growing a first set of III-N epitaxial layers coupled to the single crystal layer; growing a second set of III-N epitaxial layers coupled to the first set of III-N epitaxial layers; forming a first electronic device disposed at least partially in the first set of III-N epitaxial layers; forming a second electronic device disposed at least partially in the second set of III-N epitaxial layers; forming one or more interconnects between the first electronic device and the second electronic device; and encapsulating the first electronic device, the second electronic device, and the one or more interconnects in a chip scale package. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification