HIGH QUALITY FACTOR TIME DELAY FILTERS USING MULTI-LAYER FRINGE CAPACITORS

• US 20170310296A1
• Filed: 04/25/2017
• Published: 10/26/2017
• Est. Priority Date: 04/25/2016
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Kumu Networks, Inc.
• Inventors: Hahn, Wilhelm Steffen, Riddle, Alfred, Landi, Ernie
• Granted Patent: US 10,187,030 B2
• Time in Patent Office: Days
• CPC Class Codes: H01G 11/82 Fixing or assembling a capacitive element in a housing, e.g. mounting electrodes, current collectors or terminals in containers or encapsulations
• CPC Class Codes: H01G 4/00 Fixed capacitors; Processes of their manufacture electrolytic capacitors H01G9/00
• CPC Class Codes: H01G 4/002 Details
• CPC Class Codes: H01G 4/005 Electrodes
• CPC Class Codes: H01G 4/01 Form of self-supporting electrodes
• CPC Class Codes: H01G 4/012 Form of non-self-supporting electrodes
• CPC Class Codes: H01G 4/018 Dielectrics
• CPC Class Codes: H01G 4/228 Terminals
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H01G 4/38 Multiple capacitors, i.e. structural combinations of fixed capacitors
• CPC Class Codes: H01G 4/385 Single unit multiple capacitors, e.g. dual capacitor in one coil
• CPC Class Codes: H01G 9/008 Terminals
• CPC Class Codes: H03H 2001/0085 Multilayer, e.g. LTCC, HTCC, green sheets inside PCB filters H05K
• CPC Class Codes: H03H 7/01 Frequency selective two-port networks
• CPC Class Codes: H03H 7/0115 comprising only inductors and capacitors H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence
• CPC Class Codes: H03H 7/09 Filters comprising mutual inductance
• CPC Class Codes: H03H 7/1708 Comprising bridging elements, i.e. elements in a series path without own reference to ground and spanning branching nodes of another series path H03H7/07 takes precedence
• CPC Class Codes: H03H 7/1775 Parallel LC in shunt or branch path H03H7/1791 takes precedence
• CPC Class Codes: H03H 7/32 with lumped inductance and capacitance

Abstract

A multilayer fringe capacitor includes first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface; third and fourth interdigitated capacitor electrodes, the first and second electrodes parallel to and separated by a non-zero distance from the third and fourth electrodes; a first set of coupling vias that electrically couples the first electrode to the third electrode; and a second set of coupling vias that electrically couples the second electrode to the fourth electrode.

Claims

1. A multilayer fringe capacitor comprising:

first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface;

wherein the first electrode defines a first region within the first planar surface and the second electrode defines a second region within the first planar surface;

third and fourth interdigitated capacitor electrodes, both parallel to and intersecting a second planar surface, the second planar surface parallel to and separated by a non-zero distance from the first planar surface;

wherein the third electrode defines a third region within the second planar surface and the fourth electrode defines a fourth region within the second planar surface;

a first set of coupling vias that electrically couples the first electrode to the third electrode; and

a second set of coupling vias that electrically couples the second electrode to the fourth electrode;

wherein, upon superimposing the first planar surface upon the second planar surface, the sum of the intersection of the first and fourth regions and the intersection of the second and third regions is greater than fifty percent of the union of the first, second, third, and fourth regions.

2. The multilayer fringe capacitor of claim 1, wherein, upon superimposing the first planar surface upon the second planar surface, the sum of the intersection of the first and fourth regions and the intersection of the second and third regions is greater than eighty percent of the union of the first, second, third, and fourth regions.

3. The multilayer fringe capacitor of claim 1, having a total capacitance measured between a point on the first electrode and a point on the fourth electrode, wherein capacitance resulting from coupling between the first and third electrodes and coupling between the second and fourth electrodes contributes less than ten percent to the total capacitance.

4. The multilayer fringe capacitor of claim 3, wherein capacitance resulting from coupling between the first and third electrodes and coupling between the second and fourth electrodes contributes less than one percent to the total capacitance.

5. The multilayer fringe capacitor of claim 1, wherein the first and second electrodes have intermeshed rectangular electrode fingers;

wherein a first coupling area of the first and second electrodes comprises a first plurality of identical and adjacent cells, each cell of the first plurality including a rectangular electrode finger coupled to the first electrode and a u-shape receptacle electrode.

6. The multilayer fringe capacitor of claim 5, wherein the third and fourth electrodes have intermeshed rectangular electrode fingers;

wherein a second coupling area of the third and fourth electrodes comprises a second plurality of identical and adjacent cells, each cell of the second plurality including a rectangular electrode finger coupled to the first electrode and a u-shape receptacle electrode;

wherein cells of the first plurality are mirror images of cells of the second plurality.

7. The multilayer fringe capacitor of claim 6, wherein the rectangular electrode fingers of the cells of the first and second pluralities have aspect ratios greater than one.

8. The multilayer fringe capacitor of claim 6, wherein the rectangular electrode fingers of the cells of the first and second pluralities have aspect ratios greater than five.

9. The multilayer fringe capacitor of claim 1, wherein the multilayer fringe capacitor comprises first, second, and third layers;

wherein the first layer comprises the third and fourth electrodes;

wherein the second layer, directly above the first layer, comprises the first and second sets of coupling vias;

wherein the third layer, directly above the second layer, comprises the first and second electrodes.

10. The multilayer fringe capacitor of claim 9, further comprising a fourth layer, directly above the third layer, the fourth layer comprising an insulative material covering the first and second electrodes.

11. The multilayer fringe capacitor of claim 10, further comprising a fifth layer, directly above the fourth layer, the fifth layer comprising an auxiliary electrode.

12. The multilayer fringe capacitor of claim 11, wherein structure of the auxiliary electrode is defined by a removal of material;

wherein the removal of material is simultaneous or in iteration with capacitance measurements of the multilayer fringe capacitor, such that the removal of material changes a capacitance of the multilayer fringe capacitor from an initial value to a desired value, different from the initial value.

13. The multilayer fringe capacitor of claim 11, wherein the auxiliary electrode is coupled to a variable DC bias;

wherein the variable DC bias is changed to alter a capacitance of the multilayer fringe capacitor.

14. The multilayer fringe capacitor of claim 9, wherein the multilayer fringe capacitor is constructed from laminate;

wherein the first layer further comprises insulative prepreg material separating the third and fourth electrodes;

wherein the second layer further comprises insulative core material separating the first and second sets of vias;

wherein the third layer further comprises insulative prepreg material separating the first and second electrodes.

15. The multilayer fringe capacitor of claim 9, wherein the multilayer fringe capacitor is constructed from laminate;

wherein the first layer further comprises air separating the third and fourth electrodes;

wherein the second layer further comprises insulative core material separating the first and second sets of vias;

wherein the third layer further comprises air separating the first and second electrodes.

16. A multilayer fringe capacitor comprising:

first, second, and third capacitor electrodes, all parallel to and intersecting a first planar surface;

wherein the first electrode defines a first region within the first planar surface, the second electrode defines a second region within the first planar surface, and the third electrode defines a third region within the first planar surface;

wherein the first electrode is interdigitated with both of the second and third capacitor electrodes;

fourth, fifth, and sixth capacitor electrodes, all parallel to and intersecting a second planar surface, the second planar surface parallel to and separated a non-zero distance from the first planar surface;

wherein the fourth electrode defines a fourth region within the second planar surface, the fifth electrode defines a fifth region within the second planar surface, and the sixth electrode defines a sixth region within the second planar surface;

wherein the fourth electrode is interdigitated with both of the fifth and sixth capacitor electrodes;

a first set of coupling vias that electrically couples the first electrode to the fourth electrode;

a second set of coupling vias that electrically couples the second electrode to the fifth electrode; and

a third set of coupling vias that electrically couples the third electrode to the sixth electrode.

17. The multilayer fringe capacitor of claim 16, wherein the second and third sets of electrodes are electrically coupled by solder.

18. The multilayer fringe capacitor of claim 16, wherein the second and third sets of electrodes are removably electrically coupled by a switch.

19. A time delay filter comprising:

a substrate comprising a first isolative layer, the first isolative layer comprising a first surface and a second surface, the second surface substantially parallel to the first surface;

a resonator, comprising a capacitive element coupled to an inductive element, the inductive element comprising;

a first conductive region coupled to the first surface of the first isolative layer, a second conductive region coupled to the second surface of the first isolative layer,

a first via that is electrically coupled to and extends between the first and second conductive region;

a second via that is electrically coupled to and extends between the first conductive region and a first portion of the capacitive element; and

a third via that is electrically coupled to and extends between the second conductive region and a second portion of the capacitive element;

wherein the first conductive region, the first via, the second conductive region, the second via, the capacitive element, and the third via form a loop;

a first coupling point, electrically coupled to the first conductive region of the resonator; and

a second coupling point, electrically coupled to the second conductive region of the resonator;

wherein the capacitive element comprises;

first and second interdigitated capacitor electrodes, both parallel to and intersecting a third surface;

wherein the first electrode defines a first capacitor region within the third surface and the second electrode defines a second capacitor region within the third surface;

third and fourth interdigitated capacitor electrodes, both parallel to and intersecting a fourth surface, the fourth surface parallel to and separated by a non-zero distance from the third surface;

wherein the third electrode defines a third capacitor region within the fourth surface and the fourth electrode defines a fourth capacitor region within the fourth surface;

a first set of capacitor coupling vias that electrically couples the first electrode to the third electrode; and

a second set of capacitor coupling vias that electrically couples the second electrode to the fourth electrode;

wherein, upon superimposing the third surface upon the fourth surface, the sum of the intersection of the first and fourth capacitor regions and the intersection of the second and third capacitor regions is greater than fifty percent of the union of the first, second, third, and fourth capacitor regions.