Automatic Detection of Change in PLL Locking Trend
First Claim
1. A phase lock loop (PLL) controller, comprising:
- a clock generator configured to;
receive an error signal from a PLL, the error signal representing a difference between a frequency or a phase of a reference input signal of the PLL and a frequency or a phase of an output signal of the PLL, andgenerate a clock signal based on the error signal;
a trend detector configured to;
sample the error signal in accordance with the clock signal, anddetermine a trend of the sampled error signal; and
a trend change detector configured to;
compare the trend of the sampled error signal to a previous trend of the sampled error signal to detect for a change in the trend of the sampled error signal, andinitiate a change in a mode of operation of the PLL upon detecting the change in the trend of the sampled error signal.
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Abstract
A phase lock loop (PLL) such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal
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Citations
20 Claims
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1. A phase lock loop (PLL) controller, comprising:
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a clock generator configured to; receive an error signal from a PLL, the error signal representing a difference between a frequency or a phase of a reference input signal of the PLL and a frequency or a phase of an output signal of the PLL, and generate a clock signal based on the error signal; a trend detector configured to; sample the error signal in accordance with the clock signal, and determine a trend of the sampled error signal; and a trend change detector configured to; compare the trend of the sampled error signal to a previous trend of the sampled error signal to detect for a change in the trend of the sampled error signal, and initiate a change in a mode of operation of the PLL upon detecting the change in the trend of the sampled error signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An all-digital phase lock loop (PLL), comprising:
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a phase frequency detector (PFD) configured to compare a first frequency of a first time-varying signal represented by a digital reference input signal and a second frequency of a second time-varying signal represented by a digital output signal to provide a frequency error component of an error signal; a time-to-digital converter (TDC) configured to compare a first phase of the first time-varying signal and a second phase of the second time-varying signal to provide a phase error component of the error signal; a digital controlled oscillator (DCO) configured to adjust the second frequency and the second phase based upon the error signal; and a controller configured to; monitor the error signal to detect for a change in a trend of the error signal, and disable or enable the TDC upon detecting the change in the trend of the error signal. - View Dependent Claims (11, 12, 13, 14)
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15. A method for operating a phase lock loop (PLL), the method comprising
receiving a first error signal from the PLL in a frequency tracking mode of operation, the first error signal representing a difference between a frequency of a reference input signal of the PLL and a frequency of an output signal of the PLL; -
sampling the first error signal; determining a trend of the sampled first error signal; comparing the trend of the sampled first error signal to a previous trend of the sampled first error signal to detect for a change in the trend of the sampled first error signal; initiating a change in a mode of operation of the PLL from the frequency tracking mode of operation to a phase tracking mode of operation upon detecting the change in the trend of the sampled first error signal; and receiving a second error signal from the PLL in the phase tracking mode of operation, the second error signal representing a difference between a phase of the reference input signal and a phase of the output signal. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification