SEMICONDUCTOR DEVICE AND CORRESPONDING DEBUGGING METHOD

• US 20170315175A1
• Filed: 07/27/2016
• Published: 11/02/2017
• Est. Priority Date: 04/29/2016
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: GROSSIER, Nicolas Bernard, GUERRIERI, Lorenzo, GOBBATO, Giuseppe Livio, ZERBINI, Daniele, CORDONI, Martina, Fragneto, Pasqualina
• Granted Patent: US 10,254,338 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/28 Testing of electronic circuits, e.g. by signal tracer EMC, EMP or similar testing of electronic circuits G01R31/002; testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers or computer components G06F11/00; checking static stores for correct operation G11C29/00 ; testing receivers or transmitters of transmission systems H04B17/00
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 11/24 Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3062 where the monitored property is the power consumption power management in a computing system G06F1/3203
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/364 tracing values on a bus
• CPC Class Codes: G06F 11/3648 using additional hardware
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: H04B 2203/5495 having measurements and testing channel
• CPC Class Codes: H04B 3/54 Systems for transmission via power distribution lines
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H05B 47/185 via power line carrier transmission
• CPC Class Codes: Y02E 60/00 Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
• CPC Class Codes: Y04S 40/121 using the power network as support for the transmission

Abstract

A semiconductor device, for example an integrated circuit such as a microcontroller (MCU) or a digital signal processor (DSP), includes a semiconductor die coupled with a power supply line, a debug module coupled with the semiconductor die to exchange semiconductor die debug command and data signals with the semiconductor die, and a modem coupled with the power supply line. The debug module is arranged to convey the semiconductor die debug command and data signals over the power supply line.

Claims

1. A semiconductor device, comprising:

a power supply line;

a semiconductor die coupled with said power supply line;

a debug module coupled with said semiconductor die, wherein said debug module is arranged to exchange semiconductor die debug command and data signals with the semiconductor die; and

a modem coupled with said power supply line and said debug module, wherein said modem is arranged to exchange semiconductor die debug command and data signals over said power supply line.

2. The semiconductor device of claim 1, comprising:

a plurality of power supply pins included with said power supply line, wherein said plurality of said power supply pins are coupled to the semiconductor die, and wherein said modem is coupled with said power supply pins of the semiconductor die.

3. The semiconductor device of claim 1, wherein at least one of said debug module and said modem is included in a common package with said semiconductor die.

4. The semiconductor device of claim 1, comprising:

a support board, wherein said semiconductor die is physically coupled to said support board, the support board having a plurality of power supply terminals, wherein said modem is coupled with said power supply terminals to exchange semiconductor die debug command and data signals over said power supply line.

5. The semiconductor device of claim 4, comprising:

a second semiconductor die mounted on said support board, wherein said modem and said debug module are integrated with said second semiconductor die mounted on said support board.

6. The semiconductor device of claim 5, comprising:

a line interface arranged between said semiconductor die and said second semiconductor die.

7. The semiconductor device of claim 1, comprising:

functional circuitry formed on the semiconductor die, said functional circuitry including at least a processing unit, memory, and one or more buses, the one or more buses coupling the functional circuitry to the debug module.

8. The semiconductor device of claim 7, comprising:

a second semiconductor die having the debug module formed thereon, the semiconductor die and the second semiconductor die physically coupled together and embedded in a single package.

9. The semiconductor device of claim 8, wherein modem is formed on the second semiconductor die.

10. The semiconductor device of claim 1, wherein the semiconductor device has a package footprint which is independent of debug functionality provided by the debug module.

11. A semiconductor device debugging method, comprising:

coupling a semiconductor device to a debug system, the debug system external to said semiconductor device, the semiconductor device having at least one power supply line; and

communicating debug command and data signals between the semiconductor device and the debug system over said at least one power supply line.

12. The semiconductor device debugging method of claim 11, wherein communicating debug command and data signals between the semiconductor device and the debug system over said at least one power supply line includes communicating via a pair of powerline modems.

13. The semiconductor device debugging method of claim 12, comprising:

accepting user input via the debug system, the user input including at least one debug command;

communicating the at least one debug command via the pair of powerline modems to the semiconductor device; and

processing the at least one debug command with a debug module internal to the semiconductor device.

14. The semiconductor device debugging method of claim 12, comprising:

processing at least one debug command with a debug module internal to the semiconductor device;

capturing debug data signals generated by functional circuitry of the semiconductor device with the debug module internal to the semiconductor device; and

communicating the captured debug data signals to the debug system via the pair of powerline modems.

15. The semiconductor device debugging method of claim 11, wherein communicating debug command and data signals between the semiconductor device and the debug system over said at least one power supply line includes correcting at least some errant data signals when said errant data falls below a selected error rate.

17. The debug system of claim 11, wherein the semiconductor device has an absence of any debug pins except for the at least one power supply line.

18. The debug system of claim 11, wherein the semiconductor device is formed in a wearable device, an underwater device, or an implanted medical device.

19. The debug system of claim 11, wherein the semiconductor device is formed in a production device.

20. The debug system of claim 11, wherein at least some data communicated between the debug tool chain and the semiconductor device is compressed data.

16. A debug system, comprising:

a semiconductor device having at least one power supply line;

a debug tool chain communicatively coupled to the semiconductor device via a pair of powerline communications modems, a first one of the plurality of powerline communications modems internal to the semiconductor device and a second one of the plurality of powerline communication modems external to the semiconductor device, wherein said pair of powerline communications modems are is arranged to exchange debug command and data signals over said at least one power supply line;