ROTATIONAL GRAPHICS SUB-SLICE AND EXECUTION UNIT POWER DOWN TO IMPROVE POWER PERFORMANCE EFFICIENCY

• US 20170315607A1
• Filed: 05/08/2017
• Published: 11/02/2017
• Est. Priority Date: 09/29/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hurd, Linda L.
• Granted Patent: US 10,642,340 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus relating to rotational graphics sub-slice and Execution Unit (EU) power down to improve power performance efficiency are described. In one embodiment, power-gating is rotated amongst single sub-slices within each slice of a plurality of slices based on an indication to reduce power consumption of a computational logic. The computational logic includes the plurality of slices and each of the plurality of slices includes a plurality of sub-slices to perform one or more computations. Other embodiments are also disclosed and claimed.

Claims

1. A processor comprising:

computational logic having a plurality of slices, wherein each of the plurality of slices is to comprise a plurality of sub-slices to perform one or more computations; and

logic to cause rotation of power-gating amongst single sub-slices within each slice of the plurality of slices based on an indication to reduce power consumption of the computational logic.