DRIVE CONTROL DEVICE AND ELECTRONIC EQUIPMENT

• US 20170315659A1
• Filed: 03/16/2017
• Published: 11/02/2017
• Est. Priority Date: 04/28/2016
• Status: Active Grant

• Current Assignee: Omnivision TDDI Ontario Limited Partnership
• Original Assignee: Synaptics Japan GK (Synaptics Incorporated)
• Inventors: KUROIWA, Tsuyoshi, NOTO, Takayuki, TAKANASHI, Mitsunori
• Granted Patent: US 10,642,405 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/043 using propagating acoustic waves
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: G09G 2310/0202 Addressing of scan or signal lines
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2354/00 Aspects of interface with display user
• CPC Class Codes: G09G 2360/12 Frame memory handling
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

The drive control device includes a display control part and a touch control part. The display control part includes a control circuit operable to control first and second frame modes, and a clock pulse generator operable to produce a display line clock signal in synchronization with a display line switching cycle. The control circuit changes display and non-display drive terms in start timing on an individual display frame period basis in the first frame mode. In the second frame mode, each display frame period includes only one display drive term; the display drive term is not interrupted by a non-display drive term halfway. The second frame mode is arranged so that the cycle of the display line clock signal in synchronization with the display line switching cycle is made longer than that in the first frame mode.

Claims

1. A drive control device which drives and controls a panel module having arrays of display elements and arrays of touch detection electrodes arranged therein comprising:

a display control part which selects a display line out of the display element arrays and provides a display signal to the selected display line to perform display control in a display drive term;

a touch control part which performs touch detection control by use of the touch detection electrodes in a non-display drive term,

wherein the display control part includes a control circuit operable to control first and second frame modes, and a clock pulse generator operable to produce a display line clock signal in synchronization with a cycle of switching the display line;

wherein in the first frame mode, a non-display drive term and a display drive term are alternately created in a length of time between opposing blank terms of each display frame period multiple times, the touch control part accepts a direction for touch detection control in the non-display drive term, and the display control is performed in each display drive term;

wherein in the second frame mode, a non-display drive term and a display drive term subsequent thereto are produced in a length of time between opposing blank terms of each display frame period, and the touch control part does not accept a direction for touch detection control in the non-display drive term, and the display control is performed in the display drive term;

wherein the control circuit changes the display drive term and the non-display drive term subsequent thereto to start timing on an individual display frame period basis for every plurality of display frame periods in the case of continuing the first frame mode; and

wherein the clock pulse generator outputs the display line clock signal of a first cycle in the first frame mode, and outputs the display line clock signal of a second cycle longer than the first cycle in the second frame mode.

2. The drive control device according to claim 1, wherein:

the display control part has a scan line drive circuit operable to output scan line select clock signals for sequentially selecting the scan lines of the display elements to the panel module, and a signal line drive circuit operable to supply display drive signals to the display elements of the selected scan lines;

the scan line drive circuit changes, in pulse, the scan line select clock signals in synchronization with the display line clock signal;

the signal line drive circuit switches the display drive signals in synchronization with the display line clock signal; and

the scan line drive circuit outputs the scan line select clock signals so that a first interval from a timing of output switching of display drive signals to scan line nonselect pulse change of the scan line select clock signals remains unchanged between a case where the cycle of the display line clock signal is the first cycle and a case where the cycle of the display line clock signal is the second cycle.

3. The drive control device according to claim 2, wherein:

the first interval is a difference of a third interval from a second interval;

the scan line drive circuit changes the scan line select clock signals to scan line nonselect pulses with a timing when the second interval elapses from the pulse change of the display line clock signal; and

the signal line drive circuit switches the output of the display drive signals with a timing when the third interval elapses from the pulse change of the display line clock signal.

4. The drive control device according to claim 2, wherein the control circuit issues directions for the first and second cycles to the clock pulse generator, issues a direction for the second interval to the scan line drive circuit, and issues a direction for the third interval to the signal line drive circuit.

5. The drive control device according to claim 4, wherein the control circuit has a clock control register on which first control data for specifying the first cycle, second control data for specifying the second cycle, third control data for specifying the second interval, and fourth control data for specifying the third interval are rewritably set, and

the control circuit issues directions for the first cycle, the second cycle, the second interval and the third interval based on the first to fourth control data set on the clock control register.

6. The drive control device according to claim 5, further comprising a microprocessor operable to determine a touch or no touch based on signals obtained in touch detection control by the touch control part,

where the microprocessor sets the first to fourth control data on the clock control register.

7. The drive control device according to claim 1, wherein:

the display control part has a buffer memory into which display data are written in synchronization with an external horizontal synchronizing signal of a cycle longer than the second cycle and from which display data are read in synchronization with the display line clock signal;

the first cycle is a cycle which can assure that an intermittent read action at a speed faster than a write speed in the display drive term never brings the buffer memory with display data written therein into an empty state during each display frame period in the first frame mode; and

the second cycle is a cycle which can assure that a successive read action at a speed faster than the write speed in the display drive term never brings the buffer memory with display data written therein into the empty state during each display frame period in the second frame mode.

8. The drive control device according to claim 1, wherein the control circuit performs, as control for changing the display and non-display drive terms in start timing on an individual display frame period basis, control arranged so as to gradually increase the first display term by a predetermined length of time and shorten the last display term by the predetermined length of time in each display frame period.

9. The drive control device according to claim 1, further comprising:

a microprocessor operable to determine a touch or no touch based on signals obtained in the touch detection control by the touch control part;

wherein the display control part comprises;

a start timing register for rewritably holding fifth control data for defining the start timing of the display drive term and the start timing of the non-display drive term subsequent thereto on an individual display frame period basis for every plurality of display frame periods according to the first frame mode, and sixth control data for defining the start timing of the display drive term on an individual display frame period basis according to the second frame mode; and

a control logic which selects the fifth or sixth control data from the start timing register and produces, based on the selected control data, control signals for the corresponding display and non-display drive terms in each display frame period according to the specified display mode; and

wherein the microprocessor specifies the display mode.

10. The drive control device according to claim 9, wherein the microprocessor sets the fifth and sixth control data on the start timing register.

11. The drive control device according to claim 9, wherein the fifth and sixth control data are data which define the start timing of each of the display and non-display drive terms by a clock cycle number of the display line clock signal.

12. The drive control device according to claim 11, wherein the control logic comprises:

a first control logic which selects required data from among the fifth and sixth control data in each display frame period according to the display mode specified by the microprocessor;

a second control logic which counts up the cycle number of the display line clock signal in each display frame period and in parallel, produces status signals sequentially every time the count value reaches the start timing of each of the display and non-display drive terms in the display frame period, which the data selected by the first control logic define; and

a third control logic which receives the status signals and produces display control signals according to the received status signals; and

wherein the touch control part receives the status signals, and produces touch control signals required for the touch detection action according to the received status signals.

13. The drive control device according to claim 1, further comprising a microprocessor operable to determine a touch or no touch based on signals obtained in the touch detection control by the touch control part, wherein:

the microprocessor notifies the display control part of a second display mode in which the plurality of display frame periods are handled as one unit subsequently to its reset processing, provided that the second display mode is arranged to execute the second frame mode in part of the plurality of display frame periods, and to execute the first frame mode in the last display frame period of the plurality of display frame periods;

the microprocessor notifies the display control part of a first display mode in which the plurality of display frame periods are handled as one unit in the event of detection of a touch after notification of the second display mode, provided that the first display mode is arranged to continue the first frame mode; and

the microprocessor notifies the display control part of the second display mode in case that a given length of time has elapsed with a touch remaining undetected since the notification of the first display mode.

14. The drive control device according to claim 13 which is formed as a semiconductor integrated circuit on a semiconductor substrate.

15. A system, comprising:

a panel module having arrays of display elements and arrays of touch detection electrodes arranged therein;

a drive control device operable to drive and control the panel module; and

a host device operable to supply display data to the drive control device,

wherein the drive control device comprises;

a display control part which selects a display line out of the display element arrays and provides a display signal to the selected display line to perform display control in a display drive term;

a touch control part which performs touch detection control by use of the touch detection electrodes in a non-display drive term;

a microprocessor which determines a touch or no touch based on signals obtained in the touch detection control by the touch control part;

wherein the display control part further comprises;

a clock pulse generator operable to produce a display line clock signal in synchronization with a cycle of switching the display line;

a control circuit operable to control first and second frame modes, wherein;

in the first frame mode, a non-display drive term and a display drive term are alternately created in a length of time between opposing blank terms of each display frame period multiple times, the touch control part accepts a direction for touch detection control in the non-display drive term, and the display control is performed in each display drive term;

in the second frame mode, a non-display drive term and a display drive term subsequent thereto are produced in a length of time between opposing blank terms of each display frame period, the touch control part does not accept a direction for touch detection control in the non-display drive term, and the display control is performed in the display drive term; and

the control circuit changes the display drive term and the non-display drive term subsequent thereto in start timing on an individual display frame period basis for every plurality of display frame periods in the case of continuing the first frame mode; and

the clock pulse generator outputs the display line clock signal of a first cycle in the first frame mode, and outputs the display line clock signal of a second cycle longer than the first cycle in the second frame mode.

16. The system according to claim 15, wherein:

the display control part has a scan line drive circuit operable to output scan line select clock signals for sequentially selecting the scan lines of the display elements to the panel module, and a signal line drive circuit operable to supply display drive signals to the display elements of the selected scan lines;

the scan line drive circuit changes, in pulse, the scan line select clock signals in synchronization with the display line clock signal;

the signal line drive circuit changes the display drive signals in synchronization with the display line clock signal; and

the scan line drive circuit outputs the scan line select clock signals so that a first interval from a timing of output switching of display drive signals to scan line nonselect pulse change of the scan line select clock signals remains unchanged between a case where the cycle of the display line clock signal is the first cycle and a case where the cycle of the display line clock signal is the second cycle.

17. The system according to claim 16, wherein:

the first interval is a difference of a third interval from a second interval;

the scan line drive circuit changes the scan line select clock signals to scan line nonselect pulses with a timing when the second interval elapses from the pulse change of the display line clock signal; and

the signal line drive circuit switches the output of the display drive signals with a timing when the third interval elapses from the pulse change of the display line clock signal.

18. The system according to claim 17, wherein:

the display control part has a buffer memory into which display data are written in synchronization with an external horizontal synchronizing signal of a cycle longer than the second cycle and from which display data are read in synchronization with the display line clock signal;

the first cycle is a cycle which can assure that an intermittent read action at a speed faster than a write speed in the display drive term never brings the buffer memory with display data written therein into an empty state during each display frame period in the first frame mode; and

the second cycle is a cycle which can assure that a successive read action at a speed faster than the write speed in the display drive term never brings the buffer memory with display data written therein into the empty state during each display frame period in the second frame mode.

19. The system according to claim 18, further comprising:

a nonvolatile storage on which first control data for specifying the first cycle, second control data for specifying the second cycle, third control data for specifying the second interval, and fourth control data for specifying the third interval are stored rewritably; and

the control circuit has a clock control register on which the first to fourth control data transmitted from the nonvolatile storage are set rewritably, and issues directions for the first cycle, the second cycle, the second interval and the third interval based on the first to fourth control data set on the clock control register.

20. The system according to claim 19, wherein the microprocessor sets the first to fourth control data from the nonvolatile storage on the clock control register.