HYBRID BLOCK-BASED PROCESSOR AND CUSTOM FUNCTION BLOCKS

• US 20170315815A1
• Filed: 07/31/2016
• Published: 11/02/2017
• Est. Priority Date: 04/28/2016
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Smith, Aaron L., Gray, Jan S.
• Granted Patent: US 11,449,342 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/3818 Decoding for concurrent execution
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3873 Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Apparatus and methods are disclosed for implementing block-based processors having custom function blocks, including field-programmable gate array (FPGA) implementations. In some examples of the disclosed technology, a dynamically configurable scheduler is configured to issue at least one block-based processor instruction. A custom function block is configured to receive input operands for the instruction and generate ready state data indicating completion of a computation performed for the instruction by the respective custom function block.

Claims

1. An apparatus comprising a block-based processor, the block-based processor comprising:

an instruction scheduler configured to issue at least one instruction; and

one or more custom function blocks, the custom function blocks being configured to receive one or more input operands for the at least one instruction and generate an instruction completion signal indicating completion of a specific computation performed by the respective functional block.

2. The apparatus of claim 1, wherein the instruction completion signal comprises an instruction identifier indicating at least one instruction targeted by the at least one instruction.

3. The apparatus of claim 1, wherein the instruction completion signal comprises an instruction identifier indicating a target instruction of the at least one instruction.

4. The apparatus of claim 1, wherein the instruction scheduler issues a target instruction responsive to receiving the instruction completion signal, the instruction completion signal comprising an instruction identifier indicating the target instruction.

5. The apparatus of claim 1, wherein the custom function blocks are implemented with dynamically reconfigurable logic.

6. The apparatus of claim 1, wherein the custom function blocks can complete their respective computation in a variable number of clock cycles.

7. The apparatus of claim 1, wherein the block-based processor is configured to issue instructions out-of-order, and wherein the block-based processor is implemented using a field programmable gate array (FPGA).

8. The apparatus of claim 1, wherein:

the block-based processor comprises at least two functional units including the custom function block; and

the block-based processor is configured to issue two source operands to each of at least two functional units concurrently, each of the two source operands being designated with the same source operand slot.

9. A method of operating a configurable logic device to execute a block-based processor instruction set, the method comprising:

initiating execution of an instruction block containing a plurality of instructions encoded according to the block-based processor instruction set; and

executing one of the instructions, the executed instruction specifying use of a custom function block implemented with the configurable logic device.

10. The method of claim 9, wherein the method further comprises sending an identifier to an instruction scheduler, the identifier indicating a target instruction to receive a result generated by the custom function block.

11. The method of claim 9, wherein the custom function block comprises programmable logic devices of the configurable logic device, the method further comprising:

configuring the programmable logic devices to implement the custom function block.

12. The method of claim 11, wherein the configuring occurs before the initiating execution of the instruction block.

13. The method of claim 11, wherein the method further comprises:

delaying issue of a first instruction of a set of two or more fused instructions that has its dependencies satisfied;

determining that a second instruction of the set of fused instructions has its dependencies satisfied; and

issuing the delayed first instruction, the first instruction when executed, generating an operand consumed by the second instruction.

14. The method of claim 11, further comprising:

executing one or more instruction blocks with general-purpose execution units of the block-based processor;

based on performance data for the instruction blocks generated by a profiler, configuring the custom function block to perform a function; and

executing the instructions block with the configured custom function block.

15. The method of claim 9, wherein the configurable logic device includes an operand buffer to store instruction operands, and wherein the method further comprises:

issuing a first instruction of a set of two or more fused instructions, the first instruction specifying use of the custom function block; and

issuing a second instruction of the set of two or more fused instructions, the second instruction being issued in a sequence to allow bypass of an operand buffer.

16. The method of claim 9, wherein a function performed by the custom function block is defined at least in part based on a parameter.

17. The method of claim 16, wherein the parameter is defined by an operand of the executing instruction.

18. The method of claim 16, wherein the parameter is defined by executing a different instruction than the executing instruction.

19. A method of forming a block-based processor with a configurable logic device, the method comprising:

producing a configuration bitstream comprising configuration information for implementing a block-based processor with a configurable logic device, the block-based processor comprising;

an instruction scheduler configured to issue instructions, and

a customizable function unit configured to perform operations specified by at least a portion of the issued instructions.

20. The method of claim 19, further comprising:

based on profiler data generated by executing the instructions, dynamically and partially reconfiguring the configurable logic device to improve performance of the instructions when executed with the block-based processor.