DUAL PURPOSE BOOT REGISTERS

• US 20170315818A1
• Filed: 11/13/2014
• Published: 11/02/2017
• Est. Priority Date: 11/13/2014
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: SHIVANNA, SUHAS, SAHASRANAMAM, SRINIVASAN VARADARAJAN, SALOTAGI, NAGARAJ S
• Granted Patent: US 10,430,202 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/0787 Storage of error reports, e.g. persistent data storage, storage using memory protection
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1417 Boot up procedures
• CPC Class Codes: G06F 11/1471 involving logging of persistent data for recovery
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/2284 by power-on test, e.g. power-on self test [POST]
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 3/06 Digital input from, or digital output to, record carriers , e.g. RAID, emulated record carriers or networked record carriers
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems
• CPC Class Codes: G06F 9/441 Multiboot arrangements, i.e. selecting an operating system to be loaded

Abstract

Techniques for detecting an early boot error are provided. In one aspect, a host processor may transition to a first phase of an early boot process. The early boot process may occur before the host processor initializes a primary link between the host processor and a management controller. The host processor may then update a dual purpose boot register to store an early boot phase identifier corresponding to the first phase and an early boot status identifier corresponding to the first phase.

Claims

1. A method comprising:

transitioning, by a host processor, to a first phase of an early boot process, the early boot process occurring before the host processor initializes a primary link between the host processor and a management controller; and

updating a dual purpose boot register to store an early boot phase identifier corresponding to the first phase and an early boot status identifier corresponding to the first phase.

2. The method of claim 1, further comprising:

detecting a completion of the early boot process; and

responsive to the completion of the early boot process, using the dual purpose boot register as a scratch register.

3. The method of claim 1, wherein the dual purpose boot register is accessible to the management controller through a side-band interface.

4. The method of claim 3, wherein the side-band interface is powered by an auxiliary power source.

5. The method of claim 1, wherein the first phase identifier maps to a bit location in the dual purpose register.

6. The method of claim 1, wherein the first phase identifier maps to a value stored in a portion of the dual purpose register.

7. The method of claim 1, wherein the early boot phase identifier and the early boot status identifier are stored in the dual purpose boot register according to a platform abstraction definition.

8. The method of claim 1, further comprising:

transitioning, by the host processor, to a second phase of the early boot process; and

updating the dual purpose boot register to store a second early boot phase identifier corresponding to the second phase and a second early boot status identifier corresponding to the second phase.

9. A device comprising:

a side-band interface communicatively coupled to a host environment;

a processor coupled to the side-band interface; and

a computer-readable storage device coupled to the processor, the computer-readable storage device including instructions to cause the processor to;

obtain a boot phase identifier and boot status of the host environment based on accessing a dual purpose boot register of a host processor through the side-band interface;

store the boot phase identifier and the early boot status identifier in an early boot progress log; and

analyze the early boot progress log to detect an early boot error occurring within the host environment.

10. The device of claim 9, wherein the processor is to analyze the early boot progress log based on decoding the early boot progress log according to a platform capability abstraction definition.

11. The device of claim 10, wherein the platform capability abstraction definition specifies a mapping between the dual purpose boot register and a core within the host environment.

12. The device of claim 9, wherein the processor is to analyze the early boot progress log based on comparing the early boot progress log with a user supplied error rule.

13. The device of claim 9, wherein the processor is further to:

determine that the early boot progress log indicates a transient error; and

arm a watchdog timer to recover the system through a reset.

14. A device comprising:

a side-band interface communicatively coupled to a management controller;

a processor coupled to the side-band interface; and

a computer-readable storage device coupled to the processor, the computer-readable storage device including instructions to cause the processor to;

transition to a phase of an early boot process, the early boot process occurring before the host processor initializes a primary link between the host processor and a management controller; and

update a dual purpose boot register to store an early boot phase identifier corresponding to the first phase and an early boot status identifier corresponding to the first phase, the dual purpose register being accessible through the side-band interface.

15. The device of claim 14, wherein the side-band interface is powered by an auxiliary power source.