FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY

• US 20170315908A1
• Filed: 04/25/2017
• Published: 11/02/2017
• Est. Priority Date: 04/27/2016
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated Taiwan (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated Taiwan (Silicon Motion)
• Inventors: Yang, Tsung-Chieh, Hsu, Hong-Jung
• Granted Patent: US 9,910,772 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Claims

1. A flash memory apparatus, comprising:

a flash memory module comprising a plurality of single-level-cell blocks and at least one multiple-level-cell block; and

a flash memory controller having a plurality of channels respectively connected to the flash memory module, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) XOR (exclusive-OR) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of single-level-cell blocks;

wherein when completing program of the plurality of single-level-cell blocks, the flash memory module is arranged for performing an internal copy operation to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and the corresponding parity check code from the plurality of single-level-cell blocks to the at least one multiple-level-cell block according to an order of storing data in the plurality of single-level-cell blocks.

2. The flash memory apparatus of claim 1, wherein a cell of the at least one multiple-level-cell block is capable of storing information of 2^N bits, and N is an integer which is equal to or greater than 2;

the plurality of single-level-cell blocks are N single-level-cell blocks, and the flash memory controller is arranged for classifying the data to be programmed into N groups of data to respectively program the N groups of data into the N single-level-cell blocks.

3. The flash memory apparatus of claim 2, wherein N is equal to 3, and the at least one multiple-level-cell block is a triple-level-cell block, and the flash memory controller is arranged for classifying the data to be programmed into three groups of data to respectively program the three groups of data into three single-level-cell blocks.

4. The flash memory apparatus of claim 2, wherein when programming a group of data to a single-level-cell block, the flash memory controller is arranged for sequentially organizing and classifying every (M) word lines of all word lines of the single-level-cell block as a group of word lines to generate a plurality of odd groups of word lines and a plurality of even groups of word lines, for respectively executing different (M) exclusive-OR encoding operations upon each word line within an odd group of word lines and each word line within an even group of word lines to generate (M) partial parity check codes of the each word line within the odd group of word lines and (M) partial parity check codes of the each word line within the even group of word lines, for programming and storing (M) partial parity check codes of each word line within the plurality of odd group of word lines to last data pages of last (M) word lines in the plurality of odd group of word lines, and for programming and storing (M) partial parity check codes of each word line within the plurality of even group of word lines to last data pages of last (M) word lines in the plurality of even group of word lines.

5. The flash memory apparatus of claim 1, wherein when performing memory garbage collection, the flash memory controller is arranged for externally reading out and retrieving data from the plurality of single-level-cell blocks or from the at least one multiple-level-cell block for re-encoding and re-programming the read out and retrieved data.

6. The flash memory apparatus of claim 1, wherein when programming data into a single-level-cell block and shutdown occurring, the flash memory controller is arranged to read back data from the single-level-cell block and re-encode and program the read back data into another single-level-cell block.

7. The flash memory apparatus of claim 1, wherein when programming data into the at least one multiple-level cell block and shutdown occurring, the flash memory module is arranged to discard data stored by the at least one multiple-level cell block and perform the internal copy operation to copy and program data from the plurality of single-level-cell blocks into the at least one multiple-level cell block.

8. The flash memory apparatus of claim 1, wherein when programming data into the plurality of single-level-cell blocks, the flash memory controller is arranged to program data into the plurality of single-level-cell blocks according to a randomizer seed rule of the at least one multiple-level cell block.

9. A flash memory storage management method, comprising:

providing a flash memory module comprising a plurality of single-level-cell blocks and at least one multiple-level-cell block;

classifying data to be programmed into a plurality of groups of data;

respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) XOR (exclusive-OR) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of single-level-cell blocks; and

when completing program of the plurality of single-level-cell blocks, performing an internal copy operation to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and the corresponding parity check code from the plurality of single-level-cell blocks to the at least one multiple-level-cell block according to an order of storing data in the plurality of single-level-cell blocks.

10. The method of claim 9, wherein a cell of the at least one multiple-level-cell block is capable of storing information of 2^N bits, and N is an integer which is equal to or greater than 2;

the plurality of single-level-cell blocks are N single-level-cell blocks, and the classifying step comprises;

classifying the data to be programmed into N groups of data to respectively program the N groups of data into the N single-level-cell blocks.

11. The method of claim 10, wherein N is equal to 3, and the at least one multiple-level-cell block is a triple-level-cell block, and the step of classifying the data to be programmed into N groups of data comprises:

classifying the data to be programmed into three groups of data to respectively program the three groups of data into three single-level-cell blocks.

12. The method of claim 10, wherein the executing step comprise:

when programming a group of data to a single-level-cell block, sequentially organizing and classifying every (M) word lines of all word lines of the single-level-cell block as a group of word lines to generate a plurality of odd groups of word lines and a plurality of even groups of word lines;

respectively executing different (M) exclusive-OR encoding operations upon each word line within an odd group of word lines and upon each word line within an even group of word lines to generate (M) partial parity check codes of the each word line within the odd group of word lines and (M) partial parity check codes of the each word line within the even group of word lines; and

programming and storing (M) partial parity check codes of each word line within the plurality of odd group of word lines to last data pages of last (M) word lines in the plurality of odd group of word lines, and for programming and storing (M) partial parity check codes of each word line within the plurality of even group of word lines to last data pages of last (M) word lines in the plurality of even group of word lines.

13. The method of claim 9, further comprising:

when performing memory garbage collection, reading out and retrieving data from the plurality of single-level-cell blocks or from the at least one multiple-level-cell block for re-encoding and re-programming the read out and retrieved data.

14. The method of claim 9, further comprising:

when programming data into a single-level-cell block and shutdown occurring, reading back data from the single-level-cell block and re-encode and program the read back data into another single-level-cell block.

15. The method of claim 9, further comprising:

when programming data into the at least one multiple-level cell block and shutdown occurring, discarding data stored by the at least one multiple-level cell block and performing the internal copy operation to copy and program data from the plurality of single-level-cell blocks into the at least one multiple-level cell block.

16. The method of claim 9, further comprising:

when programming data into the plurality of single-level-cell blocks, programming data into the plurality of single-level-cell blocks according to a randomizer seed rule of the at least one multiple-level cell block.