SYSTEMS AND METHODS FOR PERFORMING DIRECT MEMORY ACCESS (DMA) OPERATIONS

• US 20170315943A1
• Filed: 04/29/2016
• Published: 11/02/2017
• Est. Priority Date: 04/29/2016
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: BENISTY, SHAY, SHARIFIE, TAL
• Application Number:
  US15/142,342
• Publication Number:
  US 20170315943A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/656 Address space sharing

Abstract

A data storage device includes a memory and a controller coupled to the memory. The controller includes an interface to enable the controller to be coupled to an access device that includes a direct memory access (DMA) engine. The controller is configured to instruct the access device to perform an access device DMA operation to transfer data from a first location of a memory of the access device to a second location of the memory of the access device.

Claims

1. A data storage device comprising:

a memory; and

a controller coupled to the memory, the controller including an interface to enable the controller to be coupled to an access device that includes a direct memory access (DMA) engine, the controller configured to instruct the access device to perform an access device DMA operation to transfer data from a first location of a memory of the access device to a second location of the memory of the access device.

2. The data storage device of claim 1, wherein the first location of the memory of the access device corresponds to one or more host buffers, and wherein the second location of the memory of the access device corresponds to a host memory buffer (HMB).

3. The data storage device of claim 1, wherein the controller includes a register to store an address of a memory element associated with the DMA engine.

4. The data storage device of claim 3, wherein the controller is configured to instruct the access device to transfer the data by sending access device DMA parameters to the access device at the address.

5. The data storage device of claim 4, wherein the controller is configured to send the access device DMA parameters to the address by sending a translation layer packet that includes a source address field, a destination address field, and a transfer size field.

6. The data storage device of claim 5, wherein the source address field identifies the first location, the destination address field identifies the second location, and the transfer size field identifies a size of the data.

7. The data storage device of claim 1, wherein the controller is configured to receive an asynchronous event request (AER) command from the access device and to instruct the access device to perform the access device DMA operation by posting a completion queue entry to a completion queue of the access device.

8. The data storage device of claim 7, wherein the completion queue entry includes access device DMA parameters to activate the DMA engine to perform the access device DMA operation.

9. The data storage device of claim 8, wherein the completion queue entry includes a command specific field, a reserved field, a submission queue identifier field, a status field, or a combination thereof, and wherein the controller is configured to populate the command specific field, the reserved field, the submission queue identifier field, the status field, or a combination thereof with the access device DMA parameters.

10. An access device comprising:

a memory;

a direct memory access (DMA) engine; and

a processor coupled to the memory and to the DMA engine, the processor, the DMA engine, or both, configured to receive access device DMA parameters from a data storage device and to initiate an access device DMA operation at the DMA engine to transfer data from a first location of the memory to a second location of the memory based on the access device DMA parameters.

11. The access device of claim 10, wherein the first location of the memory corresponds to one or more host buffers and wherein the second location of the memory corresponds to a host memory buffer (HMB).

12. The access device of claim 10, wherein the processor is further configured to send an address of a memory element associated with the DMA engine to a vendor specific register of the data storage device.

13. The access device of claim 12, wherein the processor or the DMA engine is configured to initiate the access device DMA operation responsive to a translation layer packet including the access device DMA parameters being sent by the data storage device to the memory element associated with the DMA engine.

14. The access device of claim 10, wherein the memory includes a command completion queue and wherein the processor is configured to:

send an asynchronous event request (AER) command to the data storage device; and

initiate the access device DMA operation responsive to receiving a completion queue entry that includes the access device DMA parameters being posted to the command completion queue.

15. A method comprising:

receiving, at a data storage device, a data processing instruction from an access device; and

sending access device direct memory access (DMA) parameters from the data storage device to the access device to initiate an access device DMA operation to transfer data from a first location of a memory of the access device to a second location of the memory of the access device based on the access device DMA parameters.

16. The method of claim 15, further comprising determining an address of a memory element associated with an access device DMA engine based on an address stored in a vendor specific register of the data storage device.

17. The method of claim 16, wherein sending the access device DMA parameters includes sending a translation layer packet to the address of the memory element associated with the access device DMA engine determined based on the address stored in the vendor specific register.

18. The method of claim 15, further comprising receiving an asynchronous event request (AER) command at the data storage device from the access device, and wherein sending the access device DMA parameters includes posting a completion queue entry to a completion queue of the access device.

19. The method of claim 18, wherein the completion queue entry includes a command specific field, a reserved field, a submission queue identifier field, a status field, or a combination thereof, and wherein data storage device is configured to populate the command specific field, the reserved field, the submission queue identifier field, the status field, or a combination thereof with the access device DMA parameters.

20. The method of claim 15, wherein the first location corresponds to one or more host buffers of the memory and the second location corresponds to a host memory buffer (HMB).