TFT BACKPLATE STRUCTURE AND MANUFACTURE METHOD THEREOF

• US 20170317113A1
• Filed: 07/20/2017
• Published: 11/02/2017
• Est. Priority Date: 03/04/2015
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: LV, Xiaowen, TSENG, Chihyuan, SU, Chihyu, ZHANG, Hejing
• Granted Patent: US 10,043,829 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2029/42388 characterised by the shape of the insulating material
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

A method is provided for manufacturing a thin film transistor (TFT) backplate that includes a switch TFT and a drive TFT. The method is conducted such that each of the switch TFT and the drive TFT manufactured therewith includes a source electrode/a drain electrode and a gate electrode, and also includes an etching stopper layer, a semiconductor layer, and gate isolation layer that are disposed between the source electrode/the drain electrode and the gate electrode to form a TFT structure. The gate isolation layers of the switch TFT and drive TFT are formed of different materials, such as SiOx and Al₂O₃, or SiOx and SiNx, or Al₂O₃ and a mixture of SiNx and SiOx, such that electrical properties of the switch TFT and the drive TFT are made different.

Claims

1. A manufacture method of a thin-film transistor (TFT) backplate structure, comprising the following steps:

Step 1, providing a substrate, depositing a first metal film on the substrate, and patterning the first metal film to form a first gate electrode and a second gate electrode with a distance in between;

Step 2, forming a first gate isolation layer on the substrate and the first gate electrode, and forming a second gate isolation layer on the substrate and the second gate electrode;

wherein a structure of the first gate isolation layer and a structure of the second gate isolation layer are different;

Step 3, depositing an oxide semiconductor film on the first and second gate isolation layers, and patterning the oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer;

Step 4, depositing an etching stopper film on the first and second oxide semiconductor layers and the first and second gate isolation layers, and patterning the etching stopper film to form a first etching stopper layer and a second etching stopper layer;

Step 5, depositing a second metal film on the first and second etching stopper layers and the first and second gate isolation layers, and patterning the second metal film to form a first source electrode and a first drain electrode, and a second source electrode and a second drain electrode;

wherein the first electrode and the first drain electrode are connected to the first oxide semiconductor layer and the second gate electrode, and the second electrode and the second drain electrode are connected to the second oxide semiconductor layer;

Step 6, forming a protective layer on the first source electrode and the first drain electrode and the second source electrode and the second drain electrode; and

Step 7, forming a pixel electrode on the protective layer; and

wherein the pixel electrode is connected to one of the second source electrode and the second drain electrode; and

wherein the structure of the first gate isolation layer and the structure of the second gate isolation layer are made different by having the first gate isolation layer and the second gate isolation layer made of first and second materials, respectively, the first and second materials being different from each other, wherein the first and second materials are respectively SiOx and Al₂O₃, or alternatively, the first and second materials are respectively SiOx and SiNx, or alternatively, the first and second materials are respectively Al₂O₃ and a mixture of SiNx and SiOx.

2. The manufacture method of the TFT backplate structure according to claim 1, wherein in Step 2, two masks are employed to respectively form the first gate isolation layer and the second gate isolation layer.

3. The manufacture method of the TFT backplate structure according to claim 1, wherein in Step 2, a half tone mask is employed to form the first gate isolation layer and the second gate isolation layer.

4. The manufacture method of the TFT backplate structure according to claim 1, wherein a thickness of the first gate isolation layer and a thickness of the second gate isolation layer are different.

5. The manufacture method of the TFT backplate structure according to claim 4, wherein the thickness of the first gate isolation layer is 2000 A, and the thickness of the second gate isolation layer is 4000 A.

6. A manufacture method of a thin-film transistor (TFT) backplate structure, comprising the following steps:

step 1, providing a substrate, and depositing a first metal film on the substrate, and patterning the first metal film to form a first gate electrode and a second gate electrode with a distance in between;

step 2, forming a first gate isolation layer on the on the substrate and the first gate electrode, and forming a second gate isolation layer on the substrate and the second gate electrode;

wherein a structure of the first gate isolation layer and a structure of the second gate isolation layer are different;

step 3, depositing an oxide semiconductor film on the first and second gate isolation layers, and patterning the oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer;

step 4, depositing an etching stopper film on the first and second oxide semiconductor layers and the first and second gate isolation layers, and patterning the etching stopper film to form a first etching stopper layer and a second etching stopper layer;

step 5, depositing a second metal film on the first and second etching stopper layers, and the first and second gate isolation layers, and patterning the second metal film to form a first source electrode and a first drain electrode, and a second source electrode and a second drain electrode;

wherein the first electrode and the first drain electrode are connected to the first oxide semiconductor layer and one of the first the second gate electrode, and the second electrode and the second drain electrode are connected to the second oxide semiconductor layer;

step 6, forming a protective layer on the first source electrode and the first drain electrode, and the second source electrode and the second drain electrode; and

step 7, forming a pixel electrode on the protective layer;

wherein the pixel electrode is connected to one of the second source electrode and the second drain electrode;

wherein the structure of the first gate isolation layer and the structure of the second gate isolation layer are made different by having the first gate isolation layer and the second gate isolation layer made of first and second materials, respectively, the first and second materials being different from each other, wherein the first and second materials are respectively SiOx and Al₂O₃, or alternatively, the first and second materials are respectively SiOx and SiNx, or alternatively, the first and second materials are respectively Al₂O₃ and a mixture of SiNx and SiOx;

wherein in Step 2, a half tone mask is employed to form the first gate isolation layer and the second gate isolation layer; and

a thickness of the first gate isolation layer and a thickness of the second gate isolation layer are different.

7. The manufacture method of the TFT backplate structure according to claim 6, wherein the thickness of the first gate isolation layer is 2000 A, and the thickness of the second gate isolation layer is 4000 A.