TWO-DIMENSIONAL ARRAY OF CMOS CONTROL ELEMENTS

• US 20170322291A1
• Filed: 10/14/2016
• Published: 11/09/2017
• Est. Priority Date: 05/04/2016
• Status: Active Grant

• Current Assignee: Invensense Incorporated (TDK Corporation)
• Original Assignee: Invensense Incorporated (TDK Corporation)
• Inventors: SALVIA, James Christian, PERROTT, Michael H., VOROS, Marian, NG, Eldwin, TSAI, Julius Ming-Lin, APTE, Nikhil
• Granted Patent: US 10,315,222 B2
• Time in Patent Office: Days
• CPC Class Codes: B06B 1/0622 on one surface
• CPC Class Codes: G06F 2203/0338 Fingerprint track pad, i.e. fingerprint sensor used as pointing device tracking the fingertip image
• CPC Class Codes: G06F 3/03547 Touch pads, in which fingers can move on a surface
• CPC Class Codes: G06V 40/1306 non-optical, e.g. ultrasonic or capacitive sensing
• CPC Class Codes: G06V 40/1359 Extracting features related to ridge properties; Determining the fingerprint type, e.g. whorl or loop
• CPC Class Codes: G06V 40/1376 Matching features related to ridge properties or fingerprint texture
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Abstract

An electronic device includes a plurality of CMOS control elements arranged in a two-dimensional array, where each CMOS control element of the plurality of CMOS control elements includes two semiconductor devices. The plurality of CMOS control elements include a first subset of CMOS control elements, each CMOS control element of the first subset of CMOS control elements including a semiconductor device of a first class and a semiconductor device of a second class, and a second subset of CMOS control elements, each CMOS control element of the second subset of CMOS control elements including a semiconductor device of the first class and a semiconductor device of a third class. The plurality of CMOS control elements are arranged in the two-dimensional array such that CMOS semiconductor devices of the first class are only adjacent to other CMOS semiconductor devices of the first class, CMOS semiconductor devices of the second class are only adjacent to other CMOS semiconductor devices of the second class, and CMOS semiconductor devices of the third class are only adjacent to other CMOS semiconductor devices of the third class.

Claims

1. An electronic device comprising:

a plurality of CMOS control elements arranged in a two-dimensional array, each CMOS control element of the plurality of CMOS control elements comprising two semiconductor devices, the plurality of CMOS control elements comprising;

a first subset of CMOS control elements, each CMOS control element of the first subset of CMOS control elements comprising a semiconductor device of a first class and a semiconductor device of a second class; and

a second subset of CMOS control elements, each CMOS control element of the second subset of CMOS control elements comprising a semiconductor device of the first class and a semiconductor device of a third class;

wherein the plurality of CMOS control elements are arranged in the two-dimensional array such that CMOS semiconductor devices of the first class are only adjacent to other CMOS semiconductor devices of the first class, CMOS semiconductor devices of the second class are only adjacent to other CMOS semiconductor devices of the second class, and CMOS semiconductor devices of the third class are only adjacent to other CMOS semiconductor devices of the third class.

2. The electronic device of claim 1 further comprising:

a plurality of ultrasonic transducers arranged in a two-dimensional array, each ultrasonic transducer of the plurality of ultrasonic transducers associated with a CMOS control element of the plurality of CMOS control elements.

3. The electronic device of claim 2, wherein the ultrasonic transducers are Piezoelectric Micromachined Ultrasonic Transducer (PMUT) devices.

4. The electronic device of claim 2 further comprising:

an interconnect layer disposed between the plurality of CMOS control elements and the plurality of ultrasonic transducers, the interconnect layer comprising electrical connections for electrically coupling each ultrasonic transducer to a semiconductor device of the first class, a semiconductor device of the second class, and a semiconductor device of a third class.

5. The electronic device of claim 4, wherein each ultrasonic transducer is electrically coupled to a device of the first class through a capacitor.

6. The electronic device of claim 1, wherein the semiconductor devices of the first class comprise low voltage devices, the semiconductor devices of the second class comprise high voltage PMOS devices, and the semiconductor devices of the third class comprise high voltage NMOS devices.

7. The electronic device of claim 6, wherein the semiconductor devices of the first class comprise low voltage devices comprise low voltage NMOS devices and low voltage PMOS devices.

8. The electronic device of claim 1, wherein the two-dimensional array comprises a plurality of rows comprising:

a first row comprising CMOS control elements of the first subset of CMOS control elements, wherein the semiconductor devices of the second class are adjacent to a first edge of the first row of the CMOS control elements and the semiconductor devices of the first class are adjacent to a second edge of the first row of the CMOS control elements, wherein the first edge of the first row and the second edge of the first row are opposite edges of the CMOS control elements of the first row;

a second row comprising CMOS control elements of the second subset of CMOS control elements, wherein the semiconductor devices of the first class are adjacent to a first edge of the second row of the CMOS control elements and the semiconductor devices of the third class are adjacent to a second edge of the second row of the CMOS control elements, wherein the first edge of the second row and the second edge of the second row are opposite edges of the CMOS control elements of the second row, and wherein the semiconductor devices of the first class of the second row are adjacent to the semiconductor devices of the first class of the first row;

a third row comprising CMOS control elements of the second subset of CMOS control elements, wherein the semiconductor devices of the third class are adjacent to a first edge of the third row of the CMOS control elements and the semiconductor devices of the first class are adjacent to a second edge of the third row of the CMOS control elements, wherein the first edge of the third row and the second edge of the third row are opposite edges of the CMOS control elements of the third row, and wherein the semiconductor devices of the third class of the third row are adjacent to the semiconductor devices of the third class of the second row; and

a fourth row comprising CMOS control elements of the first subset of CMOS control elements, wherein the semiconductor devices of the first class are adjacent to a first edge of the fourth row of the CMOS control elements and the semiconductor devices of the second class are adjacent to a second edge of the second row of the CMOS control elements, wherein the first edge of the fourth row and the second edge of the fourth row are opposite edges of the CMOS control elements of the fourth row, and wherein the semiconductor devices of the first class of the fourth row are adjacent to the semiconductor devices of the first class of the third row.

9. The electronic device of claim 1, wherein the two-dimensional array comprises a plurality of rows comprising:

a first pair of rows comprising CMOS control elements of the first subset of CMOS control elements, wherein CMOS control elements of a first row of the first pair of rows have reflectional symmetry with CMOS control elements of a second row of the first pair of rows relative to an adjacent edge of the first row of the first pair of rows and the second row of the first pair of rows; and

a second pair of rows comprising CMOS control elements of the second subset of CMOS control elements, wherein CMOS control elements of a first row of the second pair of rows have reflectional symmetry with CMOS control elements of a second row of the second pair of rows relative to an adjacent edge of the first row of the second pair of rows and the second row of the second pair of rows;

wherein the first pair of rows and the second pair of rows are interlaced within the two-dimensional array.

10. An electronic device comprising:

a plurality of CMOS control elements arranged in a two-dimensional array, each CMOS control element of the plurality of CMOS control elements comprising three semiconductor devices, wherein each of the three semiconductor devices is disposed in different a corner of the CMOS control element and separated by a spacing width, the semiconductor devices comprising;

a semiconductor device of a first class;

a semiconductor device of a second class; and

a semiconductor device of a third class;

wherein the plurality of CMOS control elements are arranged in the two-dimensional array such that CMOS semiconductor devices of the first class are only adjacent to other CMOS semiconductor devices of the first class, CMOS semiconductor devices of the second class are only adjacent to other CMOS semiconductor devices of the second class, and CMOS semiconductor devices of the third class are only adjacent to other CMOS semiconductor devices of the third class.

11. The electronic device of claim 10 further comprising:

a plurality of ultrasonic transducers arranged in a two-dimensional array, each ultrasonic transducer of the plurality of ultrasonic transducers associated with a CMOS control element of the plurality of CMOS control elements.

12. The electronic device of claim 11, wherein the ultrasonic transducers are Piezoelectric Micromachined Ultrasonic Transducer (PMUT) devices.

13. The electronic device of claim 11 further comprising:

an interconnect layer disposed between the plurality of CMOS control elements and the plurality of ultrasonic transducers, the interconnect layer comprising electrical connections for electrically coupling each ultrasonic transducer to a semiconductor device of the first class, a semiconductor device of the second class, and a semiconductor device of a third class.

14. The electronic device of claim 13, wherein each ultrasonic transducer is electrically coupled to a device of the first class through a capacitor.

15. The electronic device of claim 10, wherein the semiconductor devices of the first class comprise low voltage devices, the semiconductor devices of the second class comprise high voltage PMOS devices, and the semiconductor devices of the third class comprise high voltage NMOS devices.

16. The electronic device of claim 15, wherein the semiconductor devices of the first class comprise low voltage devices comprise low voltage NMOS devices and low voltage PMOS devices.

17. The electronic device of claim 10, wherein the plurality of CMOS control elements are arranged within the two-dimensional array such that the semiconductor devices within CMOS control elements having adjacent edges have reflectional symmetry relative to the adjacent edges of the CMOS control elements.

18. The electronic device of claim 10, wherein the plurality of CMOS control elements are arranged within the two-dimensional array such that the semiconductor devices within CMOS control elements having adjacent corners have 180 degree rotational symmetry relative to the adjacent corners of the CMOS control elements.

19. An electronic device comprising:

a plurality of CMOS control elements arranged in a two-dimensional array, each CMOS control element of the plurality of CMOS control elements comprising a semiconductor device, the plurality of CMOS control elements comprising;

a first subset of CMOS control elements comprising a semiconductor device of a first class;

a second subset of CMOS control elements comprising a semiconductor device of a second class; and

a third subset of CMOS control elements comprising a semiconductor device of a third class;

wherein the plurality of CMOS control elements are arranged in the two-dimensional array such that CMOS semiconductor devices of the first class are only adjacent to other CMOS semiconductor devices of the first class, CMOS semiconductor devices of the second class are only adjacent to other CMOS semiconductor devices of the second class, and CMOS semiconductor devices of the third class are only adjacent to other CMOS semiconductor devices of the third class.

20. The electronic device of claim 19 further comprising:

a plurality of ultrasonic transducers arranged in a two-dimensional array, each ultrasonic transducer of the plurality of ultrasonic transducers associated with a CMOS control element of the plurality of CMOS control elements.

21. The electronic device of claim 20, wherein the ultrasonic transducers are Piezoelectric Micromachined Ultrasonic Transducer (PMUT) devices, wherein the PMUT devices comprise center pinned membranes.

22. The electronic device of claim 20 further comprising:

an interconnect layer disposed between the plurality of CMOS control elements and the plurality of ultrasonic transducers, the interconnect layer comprising electrical connections for electrically coupling each ultrasonic transducer to a semiconductor device of the first class, a semiconductor device of the second class, and a semiconductor device of a third class.

23. The electronic device of claim 22, wherein each ultrasonic transducer is electrically coupled to a device of the first class through a capacitor.

24. The electronic device of claim 19, wherein the semiconductor devices of the first class comprise low voltage devices, the semiconductor devices of the second class comprise high voltage PMOS devices, and the semiconductor devices of the third class comprise high voltage NMOS devices.

25. The electronic device of claim 24, wherein the semiconductor devices of the first class comprise low voltage devices comprise low voltage NMOS devices and low voltage PMOS devices.

26. The electronic device of claim 19, wherein the two-dimensional array comprises a plurality of rows comprising:

a first row comprising CMOS control elements of the first subset of CMOS control elements, wherein the semiconductor devices of the first class are disposed within and span a width of the CMOS control elements of the first subset of CMOS control elements, such that the semiconductor devices of the first class of adjacent CMOS control elements of the first row are adjacent;

a second row comprising CMOS control elements of the second subset of CMOS control elements, wherein the semiconductor devices of the second class are disposed within and span a width of the CMOS control elements of the second subset of CMOS control elements, such that the semiconductor devices of the second class of adjacent CMOS control elements of the second row are adjacent; and

a third row comprising CMOS control elements of the third subset of CMOS control elements, wherein the semiconductor devices of the third class are disposed within and span a width of the CMOS control elements of the third subset of CMOS control elements, such that the semiconductor devices of the third class of adjacent CMOS control elements of the third row are adjacent.

27. The electronic device of claim 26, wherein the plurality of rows are arranged in a pattern comprising a plurality of first rows, a plurality of second rows, and a plurality of third rows, the pattern comprising:

a first row of the plurality of first rows;

a second row of the plurality of second rows;

a first row of the plurality of first rows;

a third row of the plurality of third rows; and

a first row of the plurality of first rows.

28. The electronic device of claim 26, wherein the plurality of rows are arranged in a pattern comprising a plurality of first rows, a plurality of second rows, and a plurality of third rows, the pattern comprising:

a first row of the plurality of first rows;

a second row of the plurality of second rows;

a third row of the plurality of third rows; and

a first row of the plurality of first rows.