TWO-DIMENSIONAL ARRAY OF CMOS CONTROL ELEMENTS

• US 20170322292A1
• Filed: 10/14/2016
• Published: 11/09/2017
• Est. Priority Date: 05/04/2016
• Status: Active Grant

• Current Assignee: Invensense Incorporated (TDK Corporation)
• Original Assignee: Invensense Incorporated (TDK Corporation)
• Inventors: SALVIA, James Christian, PERROTT, Michael H., VOROS, Marian, NG, Eldwin, TSAI, Julius Ming-Lin, APTE, Nikhil
• Granted Patent: US 10,325,915 B2
• Time in Patent Office: Days
• CPC Class Codes: B06B 1/0622 on one surface
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: G06F 2203/0338 Fingerprint track pad, i.e. fingerprint sensor used as pointing device tracking the fingertip image
• CPC Class Codes: G06F 3/03547 Touch pads, in which fingers can move on a surface
• CPC Class Codes: G06V 40/1306 non-optical, e.g. ultrasonic or capacitive sensing
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0925 comprising an N-well only in the substrate

Abstract

An electronic device includes a plurality of CMOS control elements arranged in a two-dimensional array, where each CMOS control element of the plurality of CMOS control elements includes semiconductor devices. The plurality of CMOS control elements each including a PMOS semiconductor device portion comprising a high voltage PMOS device and a low voltage PMOS device and an NMOS semiconductor device portion comprising a high voltage NMOS device and a low voltage NMOS device. The plurality of CMOS control elements are arranged in the two-dimensional array such that the PMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other PMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements, and such that the NMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other NMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements.

Claims

1. An electronic device comprising:

a plurality of CMOS control elements arranged in a two-dimensional array, each CMOS control element of the plurality of CMOS control elements comprising semiconductor devices, the plurality of CMOS control elements each comprising;

a PMOS semiconductor device portion comprising a high voltage PMOS device and a low voltage PMOS device; and

an NMOS semiconductor device portion comprising a high voltage NMOS device and a low voltage NMOS device;

wherein the plurality of CMOS control elements are arranged in the two-dimensional array such that the PMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other PMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements, and such that the NMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other NMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements.

2. The electronic device of claim 1 further comprising:

a plurality of ultrasonic transducers arranged in a two-dimensional array, each ultrasonic transducer of the plurality of ultrasonic transducers associated with a CMOS control element of the plurality of CMOS control elements.

3. The electronic device of claim 2, wherein the ultrasonic transducers are Piezoelectric Micromachined Ultrasonic Transducer (PMUT) devices.

4. The electronic device of claim 2 further comprising:

an interconnect layer disposed between the plurality of CMOS control elements and the plurality of ultrasonic transducers, the interconnect layer comprising electrical connections for interconnecting each ultrasonic transducer to a semiconductor device of the PMOS semiconductor device portion and to a semiconductor device of the NMOS semiconductor device portion.

5. The electronic device of claim 4, wherein the electrical connections are for interconnecting each ultrasonic transducer to a high voltage PMOS device and a low voltage PMOS device of the PMOS semiconductor device portion and to a high voltage NMOS device and a low voltage NMOS device of the NMOS semiconductor device portion.

6. The electronic device of claim 1, wherein the two-dimensional array comprises a plurality of rows of CMOS control elements, wherein adjacent rows have an alternating orientation of the CMOS control elements, such that CMOS control elements of a first row have reflectional symmetry with CMOS control elements of a second row of relative to an adjacent edge of the first row and the second row.

7. The electronic device of claim 1, wherein CMOS control elements have reflectional symmetry with adjacent CMOS control elements relative to adjacent edges.

8. An electronic device comprising:

a plurality of CMOS control elements arranged in a two-dimensional array, each CMOS control element of the plurality of CMOS control elements comprising a semiconductor device, the plurality of CMOS control elements comprising;

a first subset of CMOS control elements comprising a PMOS semiconductor device portion, the PMOS semiconductor device portion comprising a high voltage PMOS device and a low voltage PMOS device;

a second subset of CMOS control elements comprising an NMOS semiconductor device portion, the NMOS semiconductor device portion comprising a high voltage NMOS device and a low voltage NMOS device;

wherein the plurality of CMOS control elements are arranged in the two-dimensional array such that the PMOS semiconductor device portion of a CMOS control element of the first subset of CMOS control elements is only adjacent to other PMOS semiconductor device portions of adjacent CMOS control elements of the first subset of CMOS control elements, and such that the NMOS semiconductor device portion of a CMOS control element of the second subset of CMOS control elements is only adjacent to other NMOS semiconductor device portions of adjacent CMOS control elements of the second subset of CMOS control elements.

9. The electronic device of claim 8 further comprising:

a plurality of ultrasonic transducers arranged in a two-dimensional array, each ultrasonic transducer of the plurality of ultrasonic transducers associated with a CMOS control element of the plurality of CMOS control elements.

10. The electronic device of claim 9, wherein the ultrasonic transducers are Piezoelectric Micromachined Ultrasonic Transducer (PMUT) devices.

11. The electronic device of claim 9 further comprising:

an interconnect layer disposed between the plurality of CMOS control elements and the plurality of ultrasonic transducers, the interconnect layer comprising electrical connections for interconnecting each ultrasonic transducer to a semiconductor device of the PMOS semiconductor device portion and to a semiconductor device of the NMOS semiconductor device portion.

12. The electronic device of claim 11, wherein the electrical connections are for interconnecting each ultrasonic transducer to a high voltage PMOS device and a low voltage PMOS device of the PMOS semiconductor device portion and to a high voltage NMOS device and a low voltage NMOS device of the NMOS semiconductor device portion.

13. The electronic device of claim 8, wherein the two-dimensional array comprises a plurality of rows comprising:

a first row comprising CMOS control elements of the first subset of CMOS control elements, wherein the semiconductor devices of the PMOS semiconductor device portion are adjacent to a first edge of the first row of the CMOS control elements, wherein the first edge of the first row and a second edge of the first row are opposite edges of the CMOS control elements of the first row;

a second row comprising CMOS control elements of the second subset of CMOS control elements, wherein the semiconductor devices of the NMOS semiconductor device portion are adjacent to a first edge of the second row of the CMOS control elements, wherein the first edge of the second row and a second edge of the second row are opposite edges of the CMOS control elements of the second row, and wherein the second edge of the second row is adjacent to the second edge of the first row;

a third row comprising CMOS control elements of the second subset of CMOS control elements, wherein the semiconductor devices of the NMOS semiconductor device portion are adjacent to a first edge of the third row of the CMOS control elements, wherein the first edge of the third row and a second edge of the third row are opposite edges of the CMOS control elements of the third row, and wherein the first edge of the third row is adjacent to the first edge of the second row; and

a fourth row comprising CMOS control elements of the first subset of CMOS control elements, wherein the semiconductor devices of the PMOS semiconductor device portion are adjacent to a first edge of the fourth row of the CMOS control elements, wherein the first edge of the fourth row and a second edge of the fourth row are opposite edges of the CMOS control elements of the fourth row, and wherein the second edge of the fourth row is adjacent to the second edge of the third row.

14. The electronic device of claim 13, wherein the plurality of rows further comprises:

a fifth row comprising CMOS control elements of the first subset of CMOS control elements, wherein the semiconductor devices of the PMOS semiconductor device portion are adjacent to a first edge of the fifth row of the CMOS control elements, wherein the first edge of the fifth row and a second edge of the fifth row are opposite edges of the CMOS control elements of the fifth row, and wherein the first edge of the fifth row is adjacent to the first edge of the fourth row.

15. The electronic device of claim 8, wherein the two-dimensional array comprises a plurality of rows comprising:

a first pair of rows comprising CMOS control elements of the first subset of CMOS control elements, wherein CMOS control elements of a first row of the first pair of rows have reflectional symmetry with CMOS control elements of a second row of the first pair of rows relative to an adjacent edge of the first row of the first pair of rows and the second row of the first pair of rows, such that the PMOS semiconductor device portion of the first row of the first pair of rows is adjacent to the PMOS semiconductor device portion of the second row of the first pair of rows; and

a second pair of rows comprising CMOS control elements of the second subset of CMOS control elements, wherein CMOS control elements of a first row of the second pair of rows have reflectional symmetry with CMOS control elements of a second row of the second pair of rows relative to an adjacent edge of the first row of the second pair of rows and the second row of the second pair of rows, such that the NMOS semiconductor device portion of the first row of the second pair of rows is adjacent to the NMOS semiconductor device portion of the second row of the second pair of rows;

wherein the first pair of rows and the second pair of rows are interlaced within the two-dimensional array.

16. An electronic device comprising:

a plurality of CMOS control elements arranged in a two-dimensional array, each CMOS control element of the plurality of CMOS control elements comprising semiconductor devices, the plurality of CMOS control elements each comprising;

a PMOS semiconductor device portion comprising a high voltage PMOS device and a low voltage PMOS device; and

an NMOS semiconductor device portion comprising a high voltage NMOS device and a low voltage NMOS device;

a plurality of ultrasonic transducers arranged in a two-dimensional array, each ultrasonic transducer of the plurality of ultrasonic transducers associated with a CMOS control element of the plurality of CMOS control elements; and

an interconnect layer disposed between the plurality of CMOS control elements and the plurality of ultrasonic transducers, the interconnect layer comprising electrical connections for interconnecting each ultrasonic transducer to a high voltage PMOS device and a low voltage PMOS device of the PMOS semiconductor device portion and to a high voltage NMOS device and a low voltage NMOS device of the NMOS semiconductor device portion;

wherein the plurality of CMOS control elements are arranged in the two-dimensional array such that the PMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other PMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements, and such that the NMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other NMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements.

17. The electronic device of claim 16, wherein the two-dimensional array comprises a plurality of rows of CMOS control elements, wherein adjacent rows have an alternating orientation of the CMOS control elements, such that CMOS control elements of a first row have reflectional symmetry with CMOS control elements of a second row of relative to an adjacent edge of the first row and the second row.

18. The electronic device of claim 16, wherein CMOS control elements have reflectional symmetry with adjacent CMOS control elements relative to adjacent edges.

19. The electronic device of claim 16, wherein the ultrasonic transducers are Piezoelectric Micromachined Ultrasonic Transducer (PMUT) devices.

20. The electronic device of claim 19, wherein the PMUT devices comprise center pinned membranes.