Configurable Processor with In-Package Look-Up Table

• US 20170322771A1
• Filed: 05/06/2017
• Published: 11/09/2017
• Est. Priority Date: 05/06/2016
• Status: Abandoned Application

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC
• Inventors: ZHANG, Guobiao
• Application Number:
  US15/588,642
• Publication Number:
  US 20170322771A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 7/4988 by table look-up
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1776 for memories

Abstract

The present invention discloses a configurable processor with an in-package look-up table. The configurable processor comprises a programmable memory die and a logic die located in a same package. The programmable memory die comprises a look-up table circuit (LUT) for storing data related to a desired function. The logic die comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on the data read out from the LUT.

Claims

1. A configurable processor, comprising:

a programmable memory die comprising a look-up table circuit (LUT) for storing data related to a desired function;

a logic die comprising an arithmetic logic circuit (ALC) for performing arithmetic operations on said data;

a plurality of inter-die connections for communicatively coupling said memory die and said logic die;

wherein said memory die and said logic die are located in a same package.

2. The configurable processor according to claim 1, wherein said programmable memory die comprises a RAM.

3. The configurable processor according to claim 1, wherein said programmable memory die comprises a ROM.

4. The configurable processor according to claim 1, wherein said programmable memory die comprises a reprogrammable memory.

5. The configurable processor according to claim 4, wherein said LUT stores different data related to different functions during different usage cycles.

6. The configurable processor according to claim 5, wherein:

said LUT stores data related to a first function during a first usage cycle; and

said LUT stores data related to a second function during a second usage cycle.

7. The configurable processor according to claim 1, wherein said configurable processor is a configurable gate array.

8. The configurable processor according to claim 7, wherein said configurable gate array comprises a plurality of configurable computing elements.

9. The configurable processor according to claim 8, wherein each of said configurable computing elements comprises a programmable memory array for storing said data for said function.

10. The configurable processor according to claim 8, wherein each of said configurable computing elements comprises a pre-processing circuit.

11. The configurable processor according to claim 8, wherein each of said configurable computing elements comprises a post-processing circuit.

12. The configurable processor according to claim 7, wherein said configurable gate array comprises a plurality of configurable logic elements.

13. The configurable processor according to claim 12, wherein each of said configurable logic elements selectively realizes any one of a plurality of logic operations including shift, logic NOT, logic AND, logic OR, logic NOR, logic NAND, logic XOR, addition, subtraction and multiplication.

14. The configurable processor according to claim 7, wherein said configurable gate array comprises a plurality of configurable interconnects.

15. The configurable processor according to claim 14, wherein each of said configurable interconnects selectively couples or de-couples at least one interconnect line.

16. The configurable processor according to claim 1, wherein said memory die and said logic die are vertically stacked.

17. The configurable processor according to claim 1, wherein said inter-die connections comprise micro-bumps.

18. The configurable processor according to claim 1, wherein said inter-die connections comprise through-silicon vias (TSV).

19. The configurable processor according to claim 1, further comprising another programmable memory die comprising another LUT.

20. The configurable processor according to claim 19, wherein said memory die and said another memory die are vertically stacked.