Method for Reading an EEPROM and Corresponding Device

• US 20170323684A1
• Filed: 07/26/2017
• Published: 11/09/2017
• Est. Priority Date: 11/03/2015
• Status: Active Grant

• Current Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Inventors: Tailliet, Franois, Battista, Marc, Brecte, Victorien
• Granted Patent: US 10,186,320 B2
• Time in Patent Office: Days
• CPC Class Codes: B41J 2/175 Ink supply systems ; Circuit parts therefor
• CPC Class Codes: B41J 2/17523 Ink connection
• CPC Class Codes: B41J 2/17556 Means for regulating the pressure in the cartridge
• CPC Class Codes: B41J 2/17596 Ink pumps, ink valves
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.

Claims

1. A memory device comprising a read amplifier, the read amplifier comprising:

a first current generator and a second current generator;

a first inverter having an input coupled to an output of the second current generator;

a first transistor having a gate node coupled to an input node of the read amplifier, a drain node coupled to an output of the first current generator, and a source node coupled to a reference ground;

a second transistor having a gate node coupled to the output of the first current generator, a drain node coupled to a reference voltage, and a source node coupled to the gate node of the first transistor;

a third transistor having a drain node coupled to the output of the first current generator and a source node coupled to the reference ground;

a fourth transistor having a gate node coupled to the output of the first current generator, a drain node coupled to the output of the second current generator, and a source node coupled to the reference ground; and

a fifth transistor having a drain node coupled to the output of the second current generator and a source node coupled to the reference voltage.

2. The memory device of claim 1, wherein the read amplifier further comprises a second inverter having an input coupled to the output of the first inverter.

3. The memory device of claim 2, wherein the output of the second inverter is the output of the read amplifier.

4. The memory device of claim 1, wherein each of the first, second, third, and fourth transistors comprise an N-type MOSFET transistor, and wherein the fifth transistor comprises a P-t e MOSFET transistor.

5. The memory device of claim 1, further comprising a third current generator coupled to the input of the read amplifier.

6. The memory device of claim 1, further comprising a memory plane, wherein the memory plane comprises a column of memory cells coupled to a bit line, and wherein a select transistor couples the bit line to the input node of the read amplifier.

7. The memory device of claim 6, wherein each memory cell comprises a floating gate transistor coupled in series with a selection transistor, and wherein a body of the selection transistor and a body of the floating gate transistor are coupled to the reference ground.

8. The memory device of claim 6, further comprising a pre-charge circuit coupled to the bit line.

9. The memory device of claim 6, further comprising a controller with an output coupled to a gate of the select transistor.

10. A memory device comprising:

a memory plane comprising a column of memory cells, a plurality of bit lines, and a plurality of word lines;

a read amplifier configured to read the memory cells; and

a controller configured to;

pre-charge the input node of the read amplifier to a pre-charge voltage;

select a bit line and a word line associated with a memory cell of the column of memory cells; and

apply a source voltage higher than the pre-charge voltage to a source of a floating gate transistor of the memory cell to generate a read current flow from the memory cell to an input node of the read amplifier.

11. The memory device of claim 10, wherein the read amplifier is further configured to prevent a voltage present at an input of the read amplifier from falling below the pre-charge voltage when reading an erased memory cell of the memory plane.

12. The memory device of claim 10, wherein the read amplifier comprises a feedback loop circuit configured to prevent a voltage present at an input of the read amplifier from falling below the pre-charge voltage.

13. The memory device of claim 12, wherein the feedback loop circuit comprises:

a first MOSFET transistor configured in a common source configuration; and

a second MOSFET transistor configured in a source follower configuration, wherein a drain node of the first MOSFET transistor is coupled to a gate node of the second MOSFET transistor, and wherein a source node of the second MOSFET transistor is coupled to the gate node of the first MOSFET transistor and to the input of the read amplifier.

14. The memory device of claim 13, wherein the pre-charge voltage is equal to a threshold voltage of the first MOSFET transistor in the feedback loop circuit.

15. The memory device of claim 10, wherein the memory device is further configured to pre-charge the bit lines to the pre-charge voltage.

16. A method for reading a memory cell by a read amplifier, the method comprising:

selecting a word line and a bit line of the memory cell;

pre-charging the input node of the read amplifier and the bit line to a pre-charge voltage;

applying a source voltage higher than the pre-charge voltage to a source node of a floating gate transistor of the memory cell, wherein a current flows from the memory cell to the read amplifier in accordance with the applying the source voltage; and

reading, by the read amplifier, a logic value of a bit stored in the memory cell.

17. The method of claim 16, further comprising preventing a voltage at an input of the read amplifier from falling below the pre-charge voltage when reading an erased memory cell.

18. The method of claim 16, wherein the pre-charge voltage is equal to a threshold voltage of a MOSFET transistor in a feedback loop of the read amplifier.

19. The method of claim 16, further comprising applying a positive voltage to the word line and to a gate node of a MOSFET transistor, wherein the MOSFET transistor couples the bit line to the read amplifier.

20. The method of claim 16, further comprising generating, by the read amplifier, an output value corresponding to the logic value of the bit stored in the memory cell.