SEMICONDUCTOR MEMORY DEVICE INCLUDING 3-DIMENSIONAL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

• US 20170323898A1
• Filed: 09/08/2016
• Published: 11/09/2017
• Est. Priority Date: 05/04/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: OH, Sung-Lae, KIM, Jin-Ho, SON, Chang-Man, LEE, Go-Hyun, HONG, Young-Ock
• Granted Patent: US 9,837,433 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A semiconductor memory device includes a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.

Claims

1. A semiconductor memory device comprising:

a substrate comprising cell regions and a contact region between the cell regions;

a dielectric structure formed over the contact region;

a memory block having cell parts, which are respectively formed over the cell regions, a coupling part, which is formed over the contact region and couples the cell parts, and a through part, which accommodates the dielectric structure;

a peripheral circuit formed over the substrate under the memory block;

bottom wiring lines disposed between the memory block and the peripheral circuit, the bottom wiring lines being electrically coupled with the peripheral circuit;

top wiring lines disposed over the memory block; and

contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.

2. The semiconductor memory device according to claim 1, wherein the dielectric structure has an elongated shape as viewed from the top extending in a lengthwise direction of the memory block.

3. The semiconductor memory device according to claim 1, further comprising:

a slit formed between the dielectric structure and the memory block; and

a dielectric sidewall layer filled in the slit.

4. The semiconductor memory device according to claim 3, wherein the dielectric sidewall layer comprises an oxide-based material.

5. The semiconductor memory device according to claim 1, further comprising:

at least one support passing through the coupling part.

6. The semiconductor memory device according to claim 5, wherein the support comprises an oxide-based material.

7. The semiconductor memory device according to claim 1, wherein the cell parts and the coupling part comprises:

conductive lines and interlayer dielectric layers stacked alternately; and

channel layers passing through the conductive lines and the interlayer dielectric layers of the cell regions.

8. The semiconductor memory device according to claim 7, wherein the peripheral circuit comprises pass transistors for providing operating voltages to the conductive lines.

9. The semiconductor memory device according to claim 1, wherein the top wiring lines are formed of a conductive material which has a lower resistance than material forming the bottom wiring lines.

10. A method for manufacturing a semiconductor memory device, comprising:

forming a peripheral circuit over a substrate comprising cell regions and a contact region between the cell regions;

forming bottom wiring lines over the peripheral circuit the bottom wiring lines being electrically coupled with the peripheral circuit;

stacking alternating layers of interlayer dielectric layers and sacrificial layers over the bottom wiring lines;

forming a first slit for dividing the interlayer dielectric layers and the sacrificial layers of the contact region into a first portion and a second portion, wherein the first portion is continuous with the interlayer dielectric layers and the sacrificial layers of the cell region, and the second portion is isolated from the first portion and the interlayer dielectric layers and the sacrificial layers of the cell region by the first slit, thereby form a dielectric structure constructed with the second portion;

forming a dielectric sidewall layer which fills the first slit;

forming a second slit through the interlayer dielectric layers and the sacrificial layers;

removing the sacrificial layers which are exposed by the second slit;

forming a conductive material in spaces from which the sacrificial layers are removed to thereby form conductive lines;

forming contact plugs electrically coupled with the bottom wiring lines, through the dielectric structure; and

forming top wiring lines electrically coupled with the contact plugs.

11. The method according to claim 10, further comprising:

forming a through hole passing through the first portion of the interlayer dielectric layers and the sacrificial layers of the contact region, before the forming of the second slit; and

forming a support which fills the through hole.

12. The method according to claim 11, wherein the forming of the through hole is performed simultaneously with the forming of the first slit.

13. The method according to claim 11, wherein the forming of the support is performed simultaneously with the forming of the dielectric sidewall layer.

14. The method according to claim 10, wherein the support and the dielectric sidewall layer are formed of a material which has an etching selectivity different from the sacrificial layers.

15. The method according to claim 14, wherein the support and the dielectric sidewall layer are formed of an oxide-based material, and the sacrificial layers are formed of a nitride-based material.

16. The method according to claim 10, wherein the forming of the second slit is performed such that the interlayer dielectric layers and the sacrificial layers are divided into memory block units by the second slit.