THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

• US 20170323904A1
• Filed: 02/16/2017
• Published: 11/09/2017
• Est. Priority Date: 05/03/2016
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: KIM, Sung Ho, KIM, Dong Won, HUH, Jong Moo
• Granted Patent: US 10,217,767 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/10 OLED displays
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/125 including organic TFTs [OTFT]
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs

Abstract

A thin film transistor array panel includes a substrate and a thin film transistor disposed on a surface of the substrate. The thin film transistor includes a semiconductor, a source electrode, and a drain electrode that are disposed on a same layer as one another. The semiconductor is between the source electrode and the drain electrode. The thin film transistor array panel further includes a buffer layer disposed between the semiconductor and the substrate and including an inorganic insulating material. The first edge of the buffer layer is substantially parallel to an adjacent edge of the semiconductor, a second edge of the buffer layer is substantially parallel to an adjacent edge of the source electrode, and a third edge of the buffer layer is substantially parallel to an adjacent edge of the drain electrode.

Claims

1. A thin film transistor array panel comprising:

a substrate;

a thin film transistor disposed on a surface of the substrate and including a semiconductor, a source electrode, and a drain electrode that are disposed on a same layer as one another, wherein the semiconductor is between the source electrode and the drain electrode; and

a buffer layer disposed between the semiconductor and the substrate and including an inorganic insulating material,

wherein a first edge of the buffer layer is substantially parallel to an adjacent edge of the semiconductor, a second edge of the buffer layer is substantially parallel to an adjacent edge of the source electrode, and a third edge of the buffer layer is substantially parallel to an adjacent edge of the drain electrode.

2. The thin film transistor array panel of claim 1, wherein

the thin film transistor further includes a gate electrode overlapping the semiconductor and a gate insulator disposed between the gate electrode and the semiconductor, and

a boundary between the semiconductor and the source electrode or a boundary between the semiconductor and the drain electrode is substantially aligned with an adjacent side surface of the gate insulator extending in a direction substantially perpendicular to a surface of the substrate.

3. The thin film transistor array panel of claim 2, further comprising a light blocking film disposed between the buffer layer and the substrate,

wherein the light blocking film includes a part overlapping the buffer layer.

4. The thin film transistor array panel of claim 3, further comprising

an interlayer insulating layer disposed on the thin film transistor and including an insulating material,

wherein the interlayer insulating layer includes a first contact hole on the drain electrode, and a second contact hole on the light blocking film.

5. The thin film transistor array panel of claim 4, wherein the light blocking film has conductivity.

6. The thin film transistor array panel of claim 5, wherein

a depth of the first contact hole and a depth of the second contact hole are substantially equal to each other.

7. The thin film transistor array panel of claim 6, further comprising:

a first connection part disposed on the interlayer insulating layer and electrically connected to the drain electrode through the first contact hole; and

a second connection part disposed on the interlayer insulating layer and electrically connected to the light blocking film through the second contact hole.

8. The thin film transistor array panel of claim 7, wherein the first connection part and the second connection part are connected to each other.

9. The thin film transistor array panel of claim 8, further comprising:

a passivation layer disposed on the first and second connection parts,

wherein the passivation layer includes a third contact hole on one of the first connection part and the second connection part; and

a pixel electrode electrically connected to one of the first connection part and the second connection part through the third contact hole.

10. The thin film transistor array panel of claim 6, further comprising a gate conductor disposed at a same layer as the gate electrode and including substantially a same material as the gate electrode,

wherein the interlayer insulating layer includes a fourth contact hole on the gate conductor, and

a depth of the fourth contact hole is substantially the same as the depth of the first contact hole or the second contact hole.

11. A method for manufacturing a thin film transistor array panel, the method comprising:

forming a buffer layer by depositing a first insulating material on a substrate;

forming a semiconductor layer by depositing and patterning an oxide semiconductor material on the buffer layer;

forming a gate insulating layer by depositing a second insulating material on the substrate;

forming a gate conductive layer by depositing a conductive material on the gate insulating layer;

forming a photosensitive film pattern on the gate conductive layer by coating the gate conductive layer with a photoresist and patterning the photoresist through an exposure process using a mask;

etching the gate conductive layer by using the photosensitive film pattern as a mask to form a gate electrode;

etching the gate insulating layer by using the photosensitive film pattern as a mask to form a gate insulator; and

etching the buffer layer by using the semiconductor layer as a mask.

12. The method of claim 11, wherein

etching the buffer layer includes removing all sections of the buffer layer that are not covered by the semiconductor layer.

13. The method of claim 12, further comprising

forming a light blocking film on the substrate before forming the buffer layer,

wherein a part of the light blocking film is exposed during the step of etching the buffer layer.

14. The method of claim 13, further comprising

forming a source electrode and a drain electrode from part of the semiconductor layer.

15. The method of claim 14, further comprising:

forming an interlayer insulating layer by depositing a third insulating material on the substrate;

forming a first contact hole exposing the drain electrode by patterning the interlayer insulating layer through a photolithography process using one photomask; and

forming a second contact hole exposing the light blocking film by patterning the interlayer insulating layer through the photolithography process using the one photomask.

16. The method of claim 15, further comprising forming a first connection part electrically connected to the drain electrode through the first contact hole and by depositing and patterning a conductive material on the substrate after patterning the interlayer insulating layer;

and

forming a second connection part electrically connected to the light blocking film through the second contact hole by depositing and patterning the conductive material on the substrate after patterning the interlayer insulating layer,

wherein the first connection part and the second connection part are connected to each other.

17. The method of claim 16, further comprising:

forming a passivation layer on the substrate;

forming a third contact hole exposing one of the first connection part and the second connection part by patterning the passivation layer; and

forming a pixel electrode on the passivation layer, wherein the pixel electrode is electrically connected to one of the first connection part and the second connection part through the third contact hole.

18. The method of claim 15, wherein

the interlayer insulating layer includes at least one among a silicon oxide (SiOx), a silicon nitride (SiNx), and a silicon oxynitride (SiON).

19. The method of claim 15, wherein the step of forming the source electrode and the drain electrode is partially performed in at least one of the step of etching the gate insulating layer and the step of forming the interlayer insulating layer.

20. The method of claim 14, wherein the step of forming the source electrode and the drain electrode includes performing a plasma process on the semiconductor layer.

21. A thin film transistor array panel comprising:

a substrate;

a thin film transistor disposed on the substrate and including a first layer, wherein the first layer includes a semiconductor, a source electrode, and a drain electrode, wherein the semiconductor is between the source electrode and the drain electrode; and

a buffer layer disposed between the first layer and the substrate and including an inorganic insulating material,

wherein a surface area of a bottom surface of the first layer is greater than or equal to a surface area of a top surface of the buffer layer.

22. The thin film transistor array panel of claim 21, wherein the surface area of the bottom surface of the first layer is greater than or equal to a surface area of a bottom surface of the buffer layer.

23. The thin film transistor array panel of claim 22, wherein

the thin film transistor further includes a gate insulator disposed on the semiconductor, and

a boundary between the semiconductor and the source electrode and a boundary between the semiconductor and the drain electrode are each substantially aligned with a side surface of the gate insulator extending in a direction perpendicular to the surface of the substrate.

24. The thin film transistor array panel of claim 23, further comprising a light blocking film disposed between the buffer layer and the substrate, wherein the light blocking film overlaps the buffer layer.