POWER EFFICIENT HIGH SPEED LATCH CIRCUITS AND SYSTEMS
First Claim
1. A combiner latch circuit, comprising:
- an input circuit with an input A, an input B, a clock input, and an inverted clock input;
an output circuit with a differential output X, Y;
wherein the input circuit is connected to the output circuit, and configured to select a state of the output circuit from the group of;
a fourth state comprising the differential output X=1, Y=0 of the differential output X, Y; and
a fifth state comprising the differential output X=0, Y=1 of the differential output X, Y; and
wherein the input circuit is further configured to;
select the fourth state if the input A=0 and the input B=1 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fifth state; and
select the fifth state if the input A=1 and the input B=0 and the clock input encounter leading edge from 0 to 1 and the output circuit is in the fourth state.
1 Assignment
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Accused Products
Abstract
The present invention relates to a combiner latch circuit for generation of one phase differential signal pair or two phase differential signal pairs. The combiner latch circuit comprises an input circuit configured to select a state of the output circuit from a group of: a fourth state comprising the differential output X=1, Y=0, a fifth state comprising the differential output X=0, Y=1. The input circuit is further configured to select the fourth state if the input A=0 and the input B=1 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fifth state, and select the fifth state if the input A=1 and the input B=0 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fourth state.
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Citations
9 Claims
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1. A combiner latch circuit, comprising:
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an input circuit with an input A, an input B, a clock input, and an inverted clock input; an output circuit with a differential output X, Y; wherein the input circuit is connected to the output circuit, and configured to select a state of the output circuit from the group of; a fourth state comprising the differential output X=1, Y=0 of the differential output X, Y; and a fifth state comprising the differential output X=0, Y=1 of the differential output X, Y; and wherein the input circuit is further configured to; select the fourth state if the input A=0 and the input B=1 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fifth state; and select the fifth state if the input A=1 and the input B=0 and the clock input encounter leading edge from 0 to 1 and the output circuit is in the fourth state. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A latching system comprising:
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a first combiner latch circuit; a four-phase generator having a first phase output, a second phase output, a third phase output, and a fourth phase output, the four-phase generator further comprises a differential clock signal input, wherein the input A of the first combiner latch circuit is connected to the fourth phase output of the four-phase generator; wherein the input B of the first combiner latch circuit is connected to the third phase output of the four-phase generator, a differential clock signal is connected to the corresponding clock signal inputs of the first combiner latch circuit and the four-phase generator, respectively; and whereby a differential clock signal divided-by-two is provided at the output X and the output Y.
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9. The latching system according to claim 9, further comprising:
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a second combiner latch circuit; wherein the second combiner latch circuit has an input A connected to the second phase output of the four-phase generator, and an input B connected to the first phase output of the four-phase generator; and whereby a divide-by-two four-phase function is achieved at the output X and output Y of the first combiner latch circuit and output X′ and
output Y′
of the second combiner latch circuit.
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Specification