DRAM ARCHITECTURE TO REDUCE ROW ACTIVATION CIRCUITRY POWER AND PERIPHERAL LEAKAGE AND RELATED METHODS

• US 20170330609A1
• Filed: 05/11/2017
• Published: 11/16/2017
• Est. Priority Date: 05/11/2016
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Atomera Incorporated
• Inventors: Roy, Richard Stephen
• Granted Patent: US 10,109,342 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A semiconductor device may include a plurality of memory cells, and at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode, and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.

Claims

1. A semiconductor device comprising:

a plurality of memory cells;

at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions;

a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode; and

a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.

2. The semiconductor device of claim 1 wherein the first operating mode comprises an active mode, and wherein the second operating mode comprises a standby mode.

3. The semiconductor device of claim 1 wherein the at least one peripheral circuit comprises a sense amplifier.

4. The semiconductor device of claim 1 wherein the at least one peripheral circuit comprises a main wordline decoder (MWD) circuit.

5. The semiconductor device of claim 4 wherein the at least one peripheral circuit further comprises a wordline pre-decoder circuit coupled to the MWD circuitry.

6. The semiconductor device of claim 1 wherein the at least one peripheral circuit comprises an address decoder circuit.

7. The semiconductor device of claim 1 wherein the at least one peripheral circuit comprise at least one transistor comprising a source and a drain, and wherein the superlattice defines a channel between the source and the drain.

8. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

9. The semiconductor device of claim 1 wherein each base semiconductor portion comprises germanium.

10. The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

11. The semiconductor device of claim 1 wherein at least some semiconductor atoms from opposing base semiconductor portions of each superlattice layer are chemically bound together through the non-semiconductor layer therebetween.

12. A semiconductor device comprising:

a plurality of memory cells;

at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions;

a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during an active mode; and

a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a standby mode;

wherein the at least one peripheral circuit comprises a sense amplifier.

13. The semiconductor device of claim 12 wherein the at least one peripheral circuit further comprises a main wordline decoder (MWD) circuit.

14. The semiconductor device of claim 13 wherein the at least one peripheral circuit further comprises a wordline pre-decoder circuit coupled to the MWD circuitry.

15. The semiconductor device of claim 12 wherein the at least one peripheral circuit further comprises an address decoder circuit.

16. The semiconductor device of claim 12 wherein each base semiconductor portion comprises silicon, and wherein the at least one non-semiconductor monolayer comprises oxygen.

17. A method for making a semiconductor device comprising:

forming a plurality of memory cells;

forming at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions;

forming a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode; and

forming a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.

18. The method of claim 17 wherein the first operating mode comprises an active mode, and wherein the second operating mode comprises a standby mode.

19. The method of claim 17 wherein the at least one peripheral circuit comprises a sense amplifier.

20. The method of claim 17 wherein the at least one peripheral circuit comprises a main wordline decoder (MWD) circuit.

21. The method of claim 20 wherein the at least one peripheral circuit further comprises a wordline pre-decoder circuit coupled to the MWD circuitry.

22. The method of claim 17 wherein the at least one peripheral circuit comprises an address decoder circuit.

23. The method of claim 17 wherein each base semiconductor portion comprises silicon, and wherein the at least one non-semiconductor monolayer comprises oxygen.