DRAM ARCHITECTURE TO REDUCE ROW ACTIVATION CIRCUITRY POWER AND PERIPHERAL LEAKAGE AND RELATED METHODS
First Claim
1. A semiconductor device comprising:
- a plurality of memory cells;
at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions;
a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode; and
a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.
1 Assignment
0 Petitions
Accused Products
Abstract
A semiconductor device may include a plurality of memory cells, and at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode, and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.
-
Citations
23 Claims
-
1. A semiconductor device comprising:
-
a plurality of memory cells; at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions; a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode; and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A semiconductor device comprising:
-
a plurality of memory cells; at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions; a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during an active mode; and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a standby mode; wherein the at least one peripheral circuit comprises a sense amplifier. - View Dependent Claims (13, 14, 15, 16)
-
-
17. A method for making a semiconductor device comprising:
-
forming a plurality of memory cells; forming at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions; forming a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode; and forming a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode. - View Dependent Claims (18, 19, 20, 21, 22, 23)
-
Specification