HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT

• US 20170330610A1
• Filed: 04/10/2017
• Published: 11/16/2017
• Est. Priority Date: 11/11/2013
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Rajan, Suresh, Best, Scott C.
• Granted Patent: US 10,453,517 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

Claims

1. (canceled)

2. A memory controller component comprising:

a register to select a first mode or a second mode; and

transmitter circuits,

wherein the transmitter circuits, in the first mode, are to transmit data signals to a memory module over a plurality of multi-drop data-links of a first type of memory channel, and

wherein the transmitter circuits, in the second mode, are to transmit data signals to the memory module over a plurality of point-to-point data-links of a second type of memory channel.

3. The memory controller component of claim 2, wherein the memory controller component is integrated in a processor.

4. The memory controller component of claim 2, further comprising receiver circuits, wherein the receiver circuits, in the first mode, are to receive data signals from the memory module over the plurality of multi-drop data-links of the first type of memory channel, and wherein the receiver circuits, in the second mode, are to receive data signals from the memory module over the plurality of point-to-point data-links of the second type of memory channel.

5. The memory controller component of claim 2, further comprising:

additional transmitter circuits, wherein the additional transmitter circuits, in the first mode, are configured to transmit control and address (CA) signals to the memory module over a plurality of multi-drop CA-links of the first type of memory channel; and

receiver circuits, wherein the receiver circuits, in the second mode, are to receive CA signals from the memory module over a plurality of point-to-point CA-links of the second type of memory channel.

6. The memory controller component of claim 2, further comprising:

additional transmitter circuits, wherein the additional transmitter circuits, in the first mode, are configured to transmit control and address (CA) signals to the memory module over a plurality of multi-drop CA-links of the first type of memory channel; and

receiver circuits, wherein the receiver circuits, in the second mode, are to receive CA signals from the memory module over a plurality of multi-drop CA-links of the second type of memory channel.

7. The memory controller component of claim 2, further comprising additional transmitter circuit, wherein the additional transmitter circuits are configured to transmit commands to all of a plurality of modules arranged in a point-to-point configuration, wherein at least one module of the plurality of modules shares the commands with another module of the plurality of modules in the second mode.

8. The memory controller component of claim 2, wherein the transmitter circuits are configured to transmit the data signals to receiver circuits in each of nine data buffer components of the module, each of the nine data buffer components being coupled to a respective pair of at least eighteen dynamic random access memory (DRAM) devices, and each of the nine data buffer components each comprise a first mode corresponding to the first mode of the memory controller component and a second mode corresponding to the second mode of the memory controller component.

9. A memory controller component comprising

a first transmitter configured to transmit a command and address (CA) signal;

a control component to select a first mode or a second mode; and

a second transmitter,

wherein the second transmitter, when the first mode is selected by the control component, is configured to transmit a data signal over a multi-drop data-link to a first receiver and a second receiver, and

wherein the second transmitter, when the second mode is selected by the control component, is configured to transmit the data signal over a point-to-point data-link to only one of the first receiver and the second receiver.

10. The memory controller component of claim 9, wherein the control component is a control pin to select the first mode or the second mode.

11. The memory controller component of claim 9, wherein the control component is a control register to select the first mode or the second mode.

12. The memory controller component of claim 9, further comprising

a receiver configured to receive a data signal over the point-to-point data-link from a transmitter of a first memory module that is disposed in a first module socket, wherein the data signal represents data stored at the first memory module and, when accessed by the memory controller component, passes through a second memory module that is disposed in a second module socket.

13. The memory controller component of claim 12, wherein the data signal passes through one of the following of the second memory module:

a wire connection;

a pass-transistor;

an unclocked receiver-transmitter pair;

or

a clocked receiver-transmitter pair.

14. The memory controller component of claim 9, further comprising:

a first receiver configured to receive a first data signal over the point-to-point data-link from a first transmitter of a first memory module that is disposed in a first module socket, wherein the first data signal represents data stored at the first memory module and, when accessed by the memory controller component, passes through a second memory module that is disposed in a second module socket; and

a second receiver configured to receive a second data signal over a point-to-point data-link from a second transmitter of the first memory module, wherein the second data signal represents data stored at the first memory module.

15. The memory controller component of claim 9, further comprising a plurality of transmitters, including the first transmitter, the plurality of transmitters being configured to send a first command to a first address to access first data stored at a single memory module in the first mode and to send a second command to a second address to access second data stored at a plurality of memory modules in the second mode.

16. The memory controller component of claim 9, further comprising a plurality of transmitters, including the first transmitter, the plurality of transmitters being configured to send a selection of ranks to be accessed to a first memory module, wherein the first memory module shares the selection of ranks with a second memory module.

17. A memory controller component comprising:

a command and address (CA) interface comprising a plurality of transmitters;

a data interface comprising a second plurality of transmitters; and

a control register to store a value indicative of a first mode of operation of the memory controller component and a second mode of operation of the memory controller component,

wherein, during the first mode and the second mode, at least one of the plurality of transmitters sends commands to a plurality of receivers over a multi-drop link coupled between the CA interface and a plurality of memory modules,

wherein, during the first mode, at least one of the second plurality of transmitters sends data to a plurality of memory modules over a multi-drop link coupled between the data interface and the plurality of memory modules, and

wherein, during the second mode, at least one of the second plurality of transmitters sends data to a single memory module of the plurality of memory modules over a point-to-point link coupled between the data interface and the single memory module.

18. The memory controller component of claim 17,

wherein, during the first mode and the second mode, each of the plurality of transmitters sends with the plurality of receivers over the multi-drop link coupled between the CA interface and the plurality of memory modules, and

wherein, during the second mode, each of the second plurality of transmitters sends data to a single memory module over a point-to-point link coupled between the data interface and the single memory module of the plurality of memory modules.

19. The memory controller component of claim 17,

wherein the CA interface, during the first mode, initializes a first memory system in which data-links use a multi-drop topology that connects all module sockets of a motherboard substrate to the memory controller component, and

wherein the CA interface, during the second mode, initializes a second memory system in which some data-links do not connect to all module sockets of a motherboard substrate.

20. The memory controller component of claim 19, wherein the data-links of the second memory system use a point-to-point topology.

21. The memory controller component of claim 17, wherein the data interface further comprises a plurality of receivers,

wherein, during the first mode, at least one of the plurality of receivers receives data from the plurality of memory modules over a multi-drop link coupled between the data interface and the plurality of memory modules, and

wherein, during the second mode, at least one of the plurality of receivers receive data from a single memory module of the plurality of memory modules over a point-to-point link coupled between the data interface and the single memory module.