FAST SENSE AMPLIFIER WITH BIT-LINE PRE-CHARGING

• US 20170330615A1
• Filed: 01/26/2017
• Published: 11/16/2017
• Est. Priority Date: 05/10/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHOU, Chung-Cheng
• Granted Patent: US 9,812,198 B1
• Time in Patent Office: Days
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0042 Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A bit-line of a resistive memory cell includes a reference branch including a reference resistor having a predetermined value and a cell branch including an adjustable memory resistor having a variable value. The reference branch generates a reference current based on the predetermined value of the reference resistor and the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor. A sense amplifier has a first input coupled to the reference branch and a second input coupled to the cell branch. A first pre-charge transistor is coupled to a first pre-charge voltage and the cell branch. The first pre-charge transistor is configured to pre-charge the cell branch to the first pre-charge voltage prior to a read operation.

Claims

1. A resistive memory cell bit-line, comprising:

a cell branch including an adjustable memory resistor having a variable value, wherein the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor; and

a first pre-charge transistor configured to pre-charge the cell-branch to a first pre-charge voltage.

2. The resistive memory cell bit-line of claim 1, comprising a reference branch including a reference resistor having a predetermined value, wherein the reference branch generates a reference current based on the predetermined value of the reference resistor.

3. The resistive memory cell bit-line of claim 1, wherein the first pre-charge transistor is coupled between a first voltage source and the cell-branch.

4. The resistive memory cell bit-line of claim 3, wherein the first voltage source has a voltage equal to the first pre-charge voltage.

5. The resistive memory cell bit-line of claim 1, wherein a gate of the first pre-charge transistor is coupled to a read control signal.

6. The resistive memory cell bit-line of claim 1, comprising a sense amplifier having a first input coupled to the cell branch.

7. The resistive memory cell bit-line of claim 6, comprising a second pre-charge transistor coupled to the sense amplifier, wherein the second pre-charge transistor is configured to pre-charge the sense amplifier to a second pre-charge voltage.

8. The resistive memory cell bit-line of claim 1, wherein the cell branch includes at least one cascode transistor.

9. The resistive memory cell bit-line of claim 8, wherein the at least one cascode transistor includes at least one transistor having a gate coupled to a biasing voltage.

10. The resistive memory cell bit-line of claim 8, wherein the at least one cascode transistor in the cell branch includes at least one transistor having a gate coupled to a read bit signal.

11. The resistive memory cell bit-line of claim 1, wherein the first-pre charge voltage is equal to VCL-V_thn, where VCL is a clamping voltage of a clamping device of the cell branch and V_thn is a threshold voltage of the clamping device.

13. The resistive memory cell bit-line of claim 10, comprising a reference branch including a reference resistor having a predetermined value, wherein the reference branch generates a reference current based on the predetermined value of the reference resistor.

15. The resistive memory cell bit-line of claim 10, wherein the cell branch include at least one cascode transistor.

17. The resistive memory cell of claim 13, wherein the cell branch includes at least one cascode transistor.

18. The resistive memory cell of claim 17, wherein the at least one cascode transistor includes at least one transistor having a gate coupled to a biasing voltage.

19. The resistive memory cell of claim 17, wherein the at least one cascode transistor in the cell branch includes at least one transistor having a gate coupled to a read bit signal.

20. The resistive memory cell of claim 13, wherein the cell branch comprises a word-line transistor having a gate coupled to a word-line.

12. A resistive memory cell bit-line, comprising:

a cell branch including an adjustable memory resistor having a variable value, wherein the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor; and

a pre-charge transistor coupled to a pre-charge voltage and the cell branch, wherein the pre-charge transistor is configured to pre-charge the cell branch to the pre-charge voltage prior to a read operation, wherein the first-pre charge voltage is equal to VCL-V_thn, VCL is a clamping voltage of a clamping device of the cell branch and V_thn is a threshold voltage of the clamping device.

14. The resistive memory cell bit-line of claim 12, wherein a gate of the pre-charge transistor is coupled to a read control signal.

16. A resistive memory cell, comprising:

a cell branch including an adjustable memory resistor having a variable value, wherein the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor;

a sense amplifier having a first input coupled to the cell branch;

a first pre-charge transistor coupled to a first pre-charge voltage and the cell branch, wherein the first pre-charge transistor is configured to pre-charge the cell branch to the first pre-charge voltage prior to a read operation; and

a second pre-charge transistor coupled to the sense amplifier, wherein the second pre-charge transistor is configured to pre-charge an input of the sense amplifier to a second pre-charge voltage prior to a read operation.