MEMORY DEVICE HAVING VERTICAL STRUCTURE AND MEMORY SYSTEM INCLUDING THE SAME

• US 20170330624A1
• Filed: 02/15/2017
• Published: 11/16/2017
• Est. Priority Date: 05/16/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Bong-Soon Lim, Sang-Won Shim
• Inventors: Lim, Bong-soon, Shim, Sang-won
• Granted Patent: US 9,941,009 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A memory device has a vertical structure in which a row decoder, a page buffer, and a peripheral circuit are disposed under a memory cell array. The row decoder and the page buffer may be asymmetrically disposed. The peripheral circuit is disposed in an area where the row decoder and the page buffer are not disposed. The row decoder and the page buffer may be symmetrically disposed with respect to an interface of planes. The peripheral circuit may be disposed in an area including a part of the interface of the planes.

Claims

1. A memory device comprising:

a first semiconductor layer including a memory cell array that includes a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction that crosses the first direction; and

a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions such that the first semiconductor layer is on the second semiconductor layer,

the second semiconductor layer including a substrate, a plurality of row decoder circuits, a plurality of page buffer circuits, and a peripheral circuit,

the plurality of row decoder circuits at least partially overlap the memory cell array in the third direction,

the plurality of page buffer circuits at least partially overlap the memory cell array in the third direction, and

at least two row decoder circuits of the plurality of row decoder circuits have different areas or at least two page buffer circuits of the plurality of page buffer circuits have different areas.

2. The memory device of claim 1, wherein

the second semiconductor layer includes first to fourth regions sectioned by two virtual lines in the first and second directions intersecting with each other at a point overlapping the memory cell array in the third direction,

the plurality of row decoder circuits include first and second row decoder circuits, respectively, in the first and third regions,

the plurality of page buffer circuits include first and second page buffer circuits, respectively, in the second and fourth regions,

the peripheral circuit is at least one region among the first to fourth regions, and

the first and third regions have different areas from each other, or the second and fourth regions have different areas from each other.

3. The memory device of claim 2, wherein the first to fourth regions are overlapped by the memory cell array in the third direction.

4. The memory device of claim 2, wherein

the first and second regions are adjacent to each other in the second direction, and the third and fourth regions are adjacent to each other in the second direction.

5. The memory device of claim 1, wherein each of the plurality of page buffer circuits include a write circuit, a read circuit, and a plurality of latches.

7. The memory device of claim 1, wherein a number of the word lines electrically connected to a first one of the at least two row decoder circuits is different than a number of the word lines electrically connected to a second one of the at least two row decoder circuits.

8. The memory device of claim 1, wherein a number of the bit lines electrically connected to a first one of the at least two page buffer circuits is different from a number of the bit lines electrically connected to a second one of the at least two page buffer circuits.

13. The memory device of claim 2, wherein the first and second page buffer circuits are spaced apart from each other as far as possible in the second and fourth regions, respectively, or adjacent to each other at a position where the two virtual lines intersect each other.

14. The memory device of claim 2, wherein the first and second row decoder circuits are spaced apart from each other as far as possible in the first and second third regions, respectively, or adjacent to each other at a position where the two virtual lines intersect each other.

17. The memory device of claim 2, wherein

the memory cell array includes a first sub-array and a second sub-array,

the first sub-array overlaps the first and fourth regions in the third direction and is configured to be controlled by the first row decoder circuit,

the second sub-array overlaps the second and third regions in the third direction and is configured to be controlled by the second row decoder circuit,

the first page buffer circuit includes page buffer sub-circuits that are separated from each other and configured to control the first and second sub-arrays respectively, and

the second page buffer circuit includes page buffer sub-circuits that are separated from each other and configured to control the first and second sub-arrays respectively.

6. (canceled)

9-12. -12. (canceled)

15-16. -16. (canceled)

18. (canceled)

19. A memory device comprising:

a first semiconductor layer including first and second memory cell arrays that are adjacent to each other in a horizontal direction; and

a second semiconductor layer under the first semiconductor layer in a vertical direction such that the first semiconductor layer is on the second semiconductor, the second semiconductor layer including a substrate, a first row decoder circuit, and a first page buffer circuit that are configured to control the first memory cell array, a second row decoder circuit a second page buffer circuit that are configured to control the second memory cell array, and a peripheral circuit,

the first row decoder circuit and the first page buffer circuit being in a first plane region of the second semiconductor layer, the first plane region overlapping the first memory cell array in a vertical direction,

the second row decoder circuit and the second page buffer circuit being in a second plane region of the second semiconductor layer, the second plane region overlapping the second memory cell array in the vertical direction, and

the peripheral circuit including a first sub-circuit in an area of the second semiconductor layer that includes at least a part of an interface between the first and second plane regions and at least partially overlaps the first and second memory cell arrays in the vertical direction.

20. The memory device of claim 19, wherein

the first and second row decoder circuits are symmetrically arranged with respect to the interface between the first and second plane regions, and

the first and second page buffer circuits are symmetrically arranged with respect to the interface between the first and second plane regions.

21. The memory device of claim 20, wherein

the first row decoder circuit includes first and second row decoder sub-circuits separated from each other, and

the first and second row decoder sub-circuits have areas that are different from each other.

23. The memory device of claim 20, wherein

the first page buffer circuit includes first and second page buffer sub-circuits that are separated from each other, and

the first and second page buffer sub-circuits have areas that are different from each other.

26. The memory device of claim 19, wherein

the first sub-circuit includes an address buffer and a command decoder, and

the address decoder and the command decoder are configured to control the first and second row decoder circuits and the first and second page buffer circuits.

22. (canceled)

24-25. -25. (canceled)

27-30. -30. (canceled)

31. A memory device comprising:

a first semiconductor layer including a first memory cell array; and

a second semiconductor layer connected to the first semiconductor layer,

the second semiconductor layer including a plurality of row decoder circuits, a plurality of page buffer circuits, and at least one peripheral circuit,

the first semiconductor layer being on top of the second semiconductor layer,

the plurality of row decoder circuits including a first row decoder circuit and a second row decoder circuit,

the plurality of page buffer circuits including a first page buffer circuit and a second page buffer circuit,

the first memory cell array being on top of a plane region in the second semiconductor layer that includes the first row decoder circuit, the second row decoder circuit, the first page buffer circuit, the second page buffer circuit, and a portion of the at least one peripheral circuit.

32. The memory device of claim 31, wherein

an area of the first page buffer circuit is different than an area of the second page buffer circuit,

the plane region in the second semiconductor layer includes first to fourth regions sectioned by two virtual lines that intersect each other at a point underneath the first memory cell array, and

the first row decoder circuit and the second row decoder circuit are in the first region and the third region of the second semiconductor layer, respectively.

33. The memory device of claim 31, wherein

the plane region in the second semiconductor layer includes first to fourth regions sectioned by two virtual lines that intersect each other at a point underneath the first memory cell array,

the first row decoder circuit and the second row decoder circuit are in the first region and the third region of the second semiconductor layer, the at least one peripheral circuit includes a plurality of sub-circuits separately arranged in at least two regions of the first to fourth regions.

34. The memory device of claim 31, wherein

the first semiconductor layer further includes a second memory cell array adjacent to the first memory cell array in a horizontal direction,

the plane region of the second semiconductor layer is a first plane region,

the second semiconductor layer includes a second plane region under the second memory cell array,

35. The memory device of claim 31, wherein

the first memory cell array includes a plurality of strings, and

each of the plurality of strings includes a plurality of memory cells stacked on top of each other in the vertical direction.