LOW LOSS SUBSTRATE FOR HIGH DATA RATE APPLICATIONS

• US 20170330825A1
• Filed: 05/11/2016
• Published: 11/16/2017
• Est. Priority Date: 05/11/2016
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: CHOU, Yuan-Hsi, HSIEH, Tsun-Lung, WANG, Chen-Chao
• Granted Patent: US 10,236,240 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48106 the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48237 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

In one or more embodiments, a substrate includes a patterned conductive layer and a reference layer. The patterned conductive layer includes a pair of first conductive traces, a pair of second conductive traces and a reference trace between the pair of first conductive traces and the pair of second conductive traces. The reference layer is above the patterned conductive layer and defines an opening.

Claims

1. A substrate, comprising:

a first patterned conductive layer comprising;

a pair of first conductive traces;

a pair of second conductive traces; and

a first reference trace between the pair of first conductive traces and the pair of second conductive traces; and

a first reference layer above the first patterned conductive layer, the first reference layer defining an opening.

2. The substrate of claim 1, the first patterned conductive layer further comprising a third conductive trace, wherein each of the pair of first conductive traces has a first width, the third conductive trace has a second width, and the first width is greater than the second width.

3. The substrate of claim 2, wherein the second width of the third conductive trace is less than or equal to approximately 20 μ

m.

4. The substrate of claim 1, wherein each of the pair of first conductive traces has a first width greater than or equal to approximately 40 μ

m.

5. The substrate of claim 1, wherein each of the pair of first conductive traces has a first width, the first conductive traces are separated from each other by a first distance, the opening of the first reference layer has a third width greater than or equal to a quantity.

6. The substrate of claim 1, wherein each of the pair of first conductive traces has a first width, the first reference trace has a second width, the first conductive traces are separated from each other by a first distance, the first reference trace is separated from an adjacent one of the pair of first conductive traces by a second distance, and the opening of the first reference layer has a third width that is less than or equal to a quantity.

7. The substrate of claim 1, further comprising a second reference trace in the opening and above the first patterned conductive layer.

8. The substrate of claim 1, further comprising a second patterned conductive layer above the first patterned conductive layer, the second patterned conductive layer comprising a third conductive trace, wherein each of the first conductive traces has a first width, the third conductive trace has a second width, and the first width is greater than the second width.

21. The substrate of claim 1, wherein the first reference trace is a ground guard trace to reduce capacitive coupling between the pair of first conductive traces and the pair of second conductive traces of the first patterned conductive layer.

9. A substrate, comprising:

a first patterned conductive layer comprising;

a first conductive trace;

a second conductive trace; and

a first reference trace between the first conductive trace and the second conductive trace; and

a first reference layer above the first patterned conductive layer, the first reference layer defining an opening.

10. The substrate of claim 9, further comprising a second reference trace in the opening and above the first patterned conductive layer.

11. The substrate of claim 9, wherein the first conductive trace has a first width, the second conductive trace has a second width, and the first width is greater than second width.

12. The substrate of claim 11, wherein the second width of the second conductive trace is less than or equal to approximately 20 μ

m.

13. The substrate of claim 9, wherein the first conductive trace has a first width greater than or equal to approximately 40 μ

m.

14. The substrate of claim 9, further comprising a second patterned conductive layer above the first reference layer, the second patterned conductive layer comprising a third conductive trace, wherein the first conductive trace has a first width, the third conductive trace has a second width, and the first width is greater than second width.

15. The substrate of claim 14, wherein the second width of the third conductive trace is less than or equal to approximately 20 μ

m.

16. A substrate, comprising:

a first insulative layer;

a first patterned conductive layer embedded in the first insulative layer, the first patterned conductive layer comprising;

a pair of first conductive traces;

a second conductive trace; and

a first reference trace between the pair of first conductive traces and the second conductive trace; and

a first reference layer disposed on the first insulative layer and defining an opening.

17. The substrate of claim 16, wherein each of the pair of first conductive traces has a first width, the second conductive trace has a second width, and the first width is greater than the second width.

18. The substrate of claim 17, wherein the second width of the second conductive trace is less than or equal to approximately 20 μ

m.

19. The substrate of claim 16, wherein each of the pair of first conductive traces has a first width greater than or equal to approximately 40 μ

m.

20. The substrate of claim 16, further comprising a second patterned conductive layer above the first reference layer, the second patterned conductive layer comprising a third conductive trace, wherein each of the pair of first conductive traces has a first width, the third conductive trace has a second width, and the first width is greater than second width.