OPTIMIZING GATE PROFILE FOR PERFORMANCE AND GATE FILL

• US 20170330955A1
• Filed: 12/22/2014
• Published: 11/16/2017
• Est. Priority Date: 12/22/2014
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: RAHHAL-ORABI, NADIA M., GHANI, TAHIR, RACHMADY, WILLY, METZ, MATTHEW V., KAVALIEROS, JACK T., DEWEY, GILBERT, MURTHY, ANAND S., MOHAPATRA, CHANDRA S.
• Granted Patent: US 11,205,707 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Systems and methods of optimizing a gate profile for performance and gate fill are disclosed. A semiconductor device having an optimized gate profile includes a semiconductor substrate and a fin extending above the semiconductor substrate. A pair of source and drain regions are disposed on opposite sides of a channel region. A gate stack is disposed over the channel region, where the gate stack includes a top portion separated from a bottom portion by a tapered portion. The top portion and at least a portion of the tapered portion are disposed above the fm.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a fin extending above the semiconductor substrate, the fin comprising a source region and drain region located on opposite sides of a channel region;

a gate stack over the channel region, the gate stack comprising a top portion, a tapered portion and a bottom portion wherein the top portion is separated from the bottom portion by the tapered portion, wherein the top portion and at least a portion of the tapered portion are above the fin, and wherein the width of the top portion is greater than the width of the bottom portion.

2. The semiconductor device of claim 1, wherein the width of the top portion is at least two times greater than the width of the bottom portion.

3. The semiconductor device of claim 2, wherein the width of the top portion is 40 nm and the width of the bottom portion is 20 nm.

4. The semiconductor device of claim 1, wherein the tapered portion is above the fin.

5. The semiconductor device of claim 1, wherein the vertical length of the bottom portion is greater than the height of the fin.

6. The semiconductor device of claim 1, wherein the top of the tapered portion is at the midpoint of the gate stack height.

7. The semiconductor device of claim 1, wherein the tapered portion comprises curved sidewalls.

8. The semiconductor device of claim 7, wherein the curved sidewalls are concave in profile.

9. The semiconductor device of claim 1, wherein a ratio of gate height to gate length is greater than 5 to 1.

10. The semiconductor device of claim 9, wherein the ratio of gate height to gate length is 10 to 1.

11. The semiconductor device of claim 1, wherein the tapered portion is disposed below the midpoint of the gate height and above the fin.

12. The semiconductor device of claim 1, wherein the widths of the top and bottom portions are constant across the entire height of each respective portion.

13. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate having a fin extending above the semiconductor substrate;

forming a sacrificial gate structure over a channel region of the fin with a single etch process comprising a first process operation and a second process operation, the first process operation having a first processing environment and the second process operation having a second processing environment different than the first processing environment;

depositing dielectric material around the sacrificial gate structure;

removing the sacrificial gate structure to form an opening within the dielectric material having a corresponding profile of the sacrificial gate profile; and

forming a gate stack within the opening, the gate stack having the same profile as the sacrificial gate structure.

14. The method of claim 13, wherein the first process operation is a main etch operation and the second process operation is an over-etch operation.

15. The method of claim 13, wherein the first processing operation forms the top portion, and the second processing condition forms the tapered portion and the bottom portion.

16. The method of claim 13, wherein the second processing operation is performed immediately after the first processing operation.

17. The method of claim 13, wherein each processing environment comprises a processing temperature and a reactant gas concentration.

18. The method of claim 17, wherein the reactant gas concentration comprises chlorine.

19. The method of claim 17, wherein the first processing environment has a higher reactant gas concentration and a higher processing temperature than that of the second processing condition.

20. A computing device, comprising:

a motherboard;

a processor mounted on the motherboard; and

a communication chip fabricated on the same chip as the processor or mounted on the motherboard;

wherein the processor comprises a semiconductor device comprising;

a semiconductor substrate;

a fin extending above the semiconductor substrate, the fin comprising a pair of source and drain regions disposed on opposite sides of a channel region;

a gate stack disposed over the channel region, the gate stack comprising a top portion separated from a bottom portion by a tapered portion, wherein the top portion and at least a portion of the tapered portion are disposed above the fin, and wherein the width of the top portion is greater than the width of the bottom portion.

21. The semiconductor device of claim 20, wherein the width of the top portion is at least two times greater than the width of the bottom portion.

22. The semiconductor device of claim 20, wherein the tapered portion comprises curved sidewalls.

23. The semiconductor device of claim 20, wherein the curved sidewalls are concave in profile.

24. The semiconductor device of claim 20, wherein a ratio of gate height to gate length is greater than 5 to 1.

25. The semiconductor device of claim 20, wherein the tapered portion is disposed below the midpoint of the gate height and above the fin.