Techniques to Configure a Solid State Drive to Operate in a Storage Mode or a Memory Mode

• US 20170336978A1
• Filed: 06/09/2017
• Published: 11/23/2017
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: FANNING, BLAISE, SCHMISSEUR, MARK A., TETRICK, RAYMOND S., ROYER, JR., ROBERT J., MINTURN, DAVID B., MATTHEWS, SHANE
• Granted Patent: US 10,296,217 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.

Claims

1-21. -21. (canceled)

22. A method comprising:

receiving one or more configuration commands at a controller for a memory device having one or more non-volatile memory arrays; and

configuring the memory device to operate in a memory mapping mode or a combination of a direct memory access (DMA) storage mode and the memory mapping mode, based on the one or more configuration commands.

23. The method of claim 22, comprising:

setting one or more control registers associated with the memory device to indicate whether the memory device is configured to operate in the memory mapping mode or the combination of the DMA storage mode and the memory mapping mode.

24. The method of claim 22, operating the memory device in the DMA storage mode comprises providing DMA capabilities to access the one or more non-volatile memory arrays and coordinating storage of data to at least a portion of the one or more non-volatile memory arrays through a programming interface of the memory device.

25. The method of claim 22, operating the memory device in the memory mapping mode comprises causing at least a portion of the one or more non-volatile memory arrays to be addressable via a memory mapping configuration command included in the received one or more configuration commands.

26. The method of claim 22, operating the memory device in the combination of DMA storage mode and the memory mapping mode comprises:

partitioning the one or more non-volatile memory arrays such that a first portion of the one or more non-volatile memory arrays is included in a first partition and a second portion of the one or more non-volatile memory arrays is included in a second partition;

assigning the first partition to the DMA storage mode of operation; and

assigning the second partition to the memory mapping mode of operation.

27. The method of claim 22, the one or more configuration commands comprising Peripheral Component Interconnect (PCI) Express (PCIe) configuration commands arranged in compliance with PCIe Base Specification, revision 3.0 or Non-Volatile Memory Express (NVMe) Specification, revision 1.1.

28. The method of claim 27, comprising receiving the one or more configuration commands from a host computing device and operating the memory device in the memory mapping mode, the received one or more configuration commands including a PCIe or NVMe memory mapping configuration command that causes at least a portion of the one or more non-volatile memory arrays to be addressable to the host computing device for use as system memory by the host computing device.

29. The method of claim 27, comprising:

operating the memory device in a DMA storage mode at initial startup of the memory device, and responsive to receiving the one or more PCIe or NVMe configuration commands, configuring the memory device to operate in at least one of the DMA storage mode or the memory mapping mode based on the one or more PCIe or NVMe configuration commands.

30. The method of claim 22, the one or more non-volatile memory arrays comprising at least one of 3-dimensional cross-point memory, flash memory, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory, nanowire, ferroelectric transistor random access memory (FeTRAM or FeRAM), nanowire or electrically erasable programmable read-only memory (EEPROM).

31. The method of claim 22, the memory device comprising a solid state drive (SSD).

32. At least one machine readable medium comprising a plurality of instructions that in response to being executed on system cause the system to:

receive one or more configuration commands to configure a memory device having one or more non-volatile memory arrays;

configure the memory device to operate in a combination of a DMA storage mode and a memory mapping mode based on the one or more configuration commands;

partition the memory device such that a first portion of the one or more non-volatile memory arrays is included in a first partition and a second portion of the one or more non-volatile memory arrays is included in a second partition;

assign the first partition to the DMA storage mode of operation; and

assign the second partition to the memory mapping mode of operation.

33. The at least one machine readable medium of claim 32, the one or more configuration commands received from a host computing device coupled with the memory device, the one or more configuration commands comprising Peripheral Component Interconnect (PCI) Express (PCIe) configuration commands arranged in compliance with PCIe Base Specification, revision 3.0 or Non-Volatile Memory Express (NVMe) Specification, revision 1.1, the one or more configuration commands including a PCIe or NVMe memory mapping configuration command that causes at least a portion of the one or more non-volatile memory arrays to be addressable to the host computing device for use as system memory by the host computing device.

34. The at least one machine readable medium of claim 32, the memory device comprises a solid state drive (SSD).

35. An apparatus comprising:

processor circuitry at a controller for a memory device, the processor circuitry to execute logic, the logic to;

receive one or more configuration commands;

cause the memory device which has a plurality of non-volatile memory arrays to be configured to operate in at least one of a DMA storage mode or a memory mapping mode based on the received one or more configuration commands;

partition the memory device such that a first portion of the one or more non-volatile memory arrays is included in a first partition to be operated in the DMA storage mode and a second portion of the one or more non-volatile memory arrays is included in a second partition to be operated in the memory mapping mode.

36. The apparatus of claim 35, further comprising the logic to:

operate the first partition in the DMA storage mode, the logic having direct memory access (DMA) capabilities to access the one or more non-volatile memory arrays for the memory device and access to a programming interface to coordinate storage of data to at least the first portion of the one or more non-volatile memory arrays via use of the DMA capabilities; and

operate the second partition in the memory mapping mode, the logic to cause at least the second portion of the one or more non-volatile memory arrays to be addressable via a memory mapping configuration command included in the received one or more configuration commands.

37. The apparatus of claim 36, comprising the logic to cause the DMA capabilities and the programming interface to be disabled based on the one or more configuration commands including an indication to operate the memory device in only a memory mapping mode of operation.

38. The apparatus of claim 35, comprising control registers associated with the memory device, the control registers to be configured by the logic based on the received one or more configuration commands, the configured control registers to indicate whether the memory device is to operate in a DMA storage mode, a memory mapping mode or a combination of DMA storage mode and memory mapping mode.

39. The apparatus of claim 35, to cause the memory device to be configured to operate in at least one of the DMA storage mode or the memory mapping mode further comprises the logic to:

assign logical block addresses associated with the DMA storage mode, at least some of the assigned logical block addresses capable of being mapped to one or more physical memory address associated with the second portion of the one or more non-volatile memory arrays to be addressable via the memory mapping configuration command.

40. The apparatus of claim 35, the one or more configuration commands comprising Peripheral Component Interconnect (PCI) Express (PCIe) configuration commands arranged in compliance with PCIe Base Specification, revision 3.0 or Non-Volatile Memory Express (NVMe) Specification, revision 1.1.

41. The apparatus of claim 40, the one or more configuration commands received from a host system coupled to the memory device.

42. The apparatus of claim 41, the received one or more configuration commands including a PCIe or NVMe memory mapping configuration command, the logic to cause the second portion of the one or more non-volatile memory arrays to be addressable to the host system for use as system memory based on the PCIe or NVMe mapping configuration command.

43. The apparatus of claim 40, comprising the logic to:

configure the memory to initially operate in a DMA storage mode by default; and

cause the memory to be configured to operate in at least one of the DMA storage mode or the memory mapping mode based on the received one or more PCIe or NVMe configuration commands.

44. The apparatus of claim 35, the one or more non-volatile memory arrays comprising at least one of 3-dimensional cross-point memory, flash memory, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory, nanowire, ferroelectric transistor random access memory (FeTRAM or FeRAM), nanowire or electrically erasable programmable read-only memory (EEPROM).

45. The apparatus of claim 35, the memory device comprising a solid state drive (SSD).