APPARATUSES AND METHODS FOR PARALLEL WRITING TO MULTIPLE MEMORY DEVICE STRUCTURES

• US 20170336989A1
• Filed: 08/04/2017
• Published: 11/23/2017
• Est. Priority Date: 02/06/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Zawodny, Jason T., Hush, Glen E., Manning, Troy A., Finkbeiner, Timothy P.
• Granted Patent: US 10,496,286 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 29/28 Dependent multiple arrays, e.g. multi-bit arrays
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

Claims

1. An apparatus, comprising:

a memory device, wherein the memory device comprises;

an array of memory cells;

sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and a compute component configured to implement logical operations; and

a memory controller coupled to the array and sensing circuitry, the memory controller configured to;

receive a block of resolved instructions; and

write the resolved instructions to a plurality of locations in the array in parallel.

2. The apparatus of claim 1, where the memory controller is configured to:

receive resolved constant data; and

write the resolved constant data to a plurality of locations in the array in parallel.

4. The apparatus of claim 1, wherein the memory controller is configured to use a DRAM protocol and DRAM logical and electrical interfaces to receive the resolved instructions and/or constant data from a host.

5. The apparatus of claim 4, wherein the apparatus comprises a bank arbiter, wherein the bank arbiter is configured to:

address translate a received multicast command; and

send the resolved instructions and/or constant data to a bank associated with the memory controller in order to write to a plurality of locations in the bank in parallel.

6. The apparatus of claim 5, wherein the bank arbiter is configured to address translate the multicast command using a series of registers associated with the bank arbiter.

7. The apparatus of claim 5, wherein the bank arbiter is configured to receive the multicast command via a channel controller coupled to the host.

8. The apparatus of claim 1, wherein the apparatus comprises a bank arbiter coupled to a plurality of banks in the memory device, and wherein the bank arbiter is configured to:

receive a multicast command via an augmented dynamic random access memory (DRAM) command protocol; and

wherein the augmented DRAM command protocol is received using a DRAM control bus coupled the memory device.

9. The apparatus of claim 8, wherein the augmented DRAM command protocol indicates to the bank arbiter that writes are to be performed in a multicast manner.

10. The apparatus of claim 1, wherein the apparatus comprises a bank arbiter coupled to a plurality of banks in the memory device and the bank arbiter comprises logic to set bank address bits and row address bits in a series of registers for a plurality of locations in the plurality of banks.

11. The apparatus of claim 10, wherein the bank arbiter is configured to:

receive a multicast write command via a DRAM control bus coupled to the memory device;

read the series of registers; and

send the resolved instructions and/or constant data to a relevant memory controller to write in parallel to the plurality of locations.

12. The apparatus of claim 1, wherein the resolved instructions include processor-in-memory (PIM) commands.

3. (canceled)

13. An apparatus, comprising:

a memory device, wherein the memory device comprises a plurality of banks coupled to a bank arbiter, the bank arbiter configured to;

receive a multicast command;

read registers associated with the multicast command; and

send resolved instructions and/or constant data to the selected banks of the plurality of banks, wherein each bank comprises;

an array of memory cells;

sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and a compute component configured to implement logical operations; and

a memory controller coupled to the array and the sensing circuitry, wherein the memory controller is configured to;

receive resolved instructions and/or constant data sent to the bank; and

write the resolved instructions and/or constant data to the bank.

14. The apparatus of claim 13, wherein the memory controller is configured to write the resolved instructions and/or constant data to a plurality of subarrays in the selected banks of the respective plurality of banks.

15. The apparatus of claim 14, wherein the plurality of subarrays are different among select ones of the plurality of banks.

16. The apparatus of claim 13, wherein the apparatus comprises a plurality of memory devices coupled to the host via a channel controller, wherein the apparatus is configured to:

receive the multicast command to relevant bank arbiters, among the plurality of memory devices, from the channel controller;

receive the multicast command to relevant memory controllers, among the selected banks of the plurality of banks of the respective memory device.

17. (canceled)

18. (canceled)

19. An apparatus, comprising:

a channel controller coupled to a plurality of memory devices, the channel controller configured to send a multicast command to the plurality of memory devices; and

a bank arbiter for each memory device coupled to the channel controller, each bank arbiter coupled to a plurality of banks in the respective memory device, each bank arbiter configured to;

receive the multicast command from the channel controller;

read registers associated with the bank arbiter responsive to the received multicast command; and

send resolved instructions and/or constant data to a selected bank of the plurality of banks based on the read registers; and

wherein each bank comprises;

an array of memory cells;

sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and a compute component configured to implement logical operations; and

a memory controller coupled to the array and the sensing circuitry, wherein the memory controller is configured to perform a data write operation to the selected bank of the plurality of banks.

20. The apparatus of claim 19, wherein the resolved instructions and/or constant data are address translated by the channel controller.

21. The apparatus of claim 19, wherein the memory controller is configured to control the sensing circuitry to:

implement logical functions including AND, OR, NOT, XOR, NAND, and NOR logical functions; and

perform non-Boolean logic operations including copy, compare and erase.

23. The apparatus of claim 19, wherein:

the array of memory cells are dynamic random access memory (DRAM) cells and the data write operation to the selected bank is to a plurality of subarrays in the selected bank;

the memory controller is configured to use a DRAM protocol and DRAM logical and electrical interfaces for non-multicast write operations; and

the channel controller is configured to send an augmented DRAM command to the bank arbiter in the respective memory device to indicate when a multicast write operation is to be performed.

22. (canceled)

24. A method for operating a memory device to parallel write to a plurality of locations, comprising:

receiving resolved instructions and/or constant data to the memory device, wherein the memory device comprises;

an array of memory cells;

sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to implement logical operations; and

a memory controller coupled to the array and the sensing circuitry; and

writing the resolved instructions and/or constant data to the plurality of locations in the memory device.

25. The method of claim 24, wherein the method comprises performing a multicast write operation to write the resolved instructions and/or constant data to a plurality of banks of the memory device in parallel.

26. The method of claim 25, wherein the method comprises writing the resolved instructions and/or constant data to a plurality of subarrays among the plurality of banks of the memory device in parallel.

27. The method of claim 26, wherein the method comprises writing the resolved instructions and/or constant data to a plurality of different subarrays among the plurality of banks of the memory device in parallel.

28. A method for operating a memory device to parallel write to a plurality of locations, comprising:

receiving resolved instruction and/or constant data to the memory device, wherein the memory device comprises;

an array of memory cells;

sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to implement logical operations; and

a memory controller coupled to the array and the sensing circuitry; and

receiving a multicast write command; and

performing a multicast write operation to send the resolved instructions and/or constant data to the plurality of locations in the memory device.

29. The method of claim 28, wherein the method comprises:

writing the resolved instructions and/or constant data to a plurality of memory devices; and

wherein writing the resolved instructions and/or constant data comprises writing resolved instructions and/or constant data associated with processing in memory (PIM) commands to the plurality of memory devices.

30. The method of claim 29, wherein the method comprises:

receiving the multicast write command at the memory controller; and

reading a series of registers set on the memory controller to send the resolved instructions and/or constant data to a plurality of subarrays in a bank associated with the memory controller.

31. The method of claim 30, wherein receiving the multicast write command comprises receiving an augmented dynamic random access memory (DRAM) write command at the memory controller from a channel controller.

32-36. -36 (canceled)