Memory Systems, Modules, and Methods for Improved Capacity
First Claim
1. A memory system comprising:
- a controller component to issue memory commands and communicate data via a controller interface; and
memory modules, including a first memory module and a second memory module, each memory module having;
a module data interface connected to the controller interface via point-to-point data connections to communicate a subset of the data;
at least one delay-configurable data buffer coupled to the module data interface to communicate the subset of the data;
memory devices coupled to the at least one data buffer to store and convey the subset of the data;
a command input port to receive the memory commands from the controller component;
a command relay circuit coupled to the command port to convey the memory commands from the memory module; and
command logic coupled to the command port to receive the memory commands from the controller, the command logic to issue commands to the memory devices responsive to the memory commands.
1 Assignment
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Accused Products
Abstract
A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.
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Citations
20 Claims
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1. A memory system comprising:
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a controller component to issue memory commands and communicate data via a controller interface; and memory modules, including a first memory module and a second memory module, each memory module having; a module data interface connected to the controller interface via point-to-point data connections to communicate a subset of the data; at least one delay-configurable data buffer coupled to the module data interface to communicate the subset of the data; memory devices coupled to the at least one data buffer to store and convey the subset of the data; a command input port to receive the memory commands from the controller component; a command relay circuit coupled to the command port to convey the memory commands from the memory module; and command logic coupled to the command port to receive the memory commands from the controller, the command logic to issue commands to the memory devices responsive to the memory commands. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 13)
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10. A memory module comprising:
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a module data interface to communicate data signals external to the memory module; at least one delay-configurable data buffer coupled to the module data interface to selectively delay the data signals; memory devices coupled to the at least one data buffer to store and convey the selectively delayed data signals; a command input port to receive the memory commands from the controller component; a command relay circuit coupled to the command port to convey the memory commands from the memory module; and command logic coupled to the command port to receive the memory commands from the controller, the command logic to issue commands to the memory devices responsive to the memory commands. - View Dependent Claims (11, 12, 14, 15)
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16. A method of communicating with first memory devise on a first memory module and second devices on a second memory module, the method comprising:
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issuing a command to the first of the memory module; delaying the command on the first memory module by a delay to produce a first delayed command; relaying the command through the first memory module to the second memory module, the relaying introducing the delay in the command to produce a second delayed command; issuing the first delayed command to the first memory devices on the first memory module; and issuing the second delayed command to the second memory devices on the second memory module. - View Dependent Claims (17, 18, 19, 20)
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Specification