SYSTEM AND METHOD FOR MEMORY SYNCHRONIZATION OF A MULTI-CORE SYSTEM

• US 20170337256A1
• Filed: 08/04/2017
• Published: 11/23/2017
• Est. Priority Date: 02/04/2015
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: ILIOPOULOS, Antonios, GOIKHMAN, Shay, LEVY, Eliezer
• Granted Patent: US 10,452,686 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 16/2315 Optimistic concurrency control
• CPC Class Codes: G06F 16/27 Replication, distribution or synchronisation of data between databases or within a distributed database system; Distributed database system architectures therefor
• CPC Class Codes: G06F 16/283 Multi-dimensional databases or data warehouses, e.g. MOLAP or ROLAP
• CPC Class Codes: G06F 2212/682 Multiprocessor TLB consistency

Abstract

A system for memory synchronization of a multi-core system is provided, the system comprising: an assigning module which is configured to assign at least one memory partition to at least one core of the multi-core system; a mapping module which is configured to provide information for translation lookaside buffer shootdown for the multi-core system leveraged by sending an interrupt to the at least one core of the multi-core system, if a page table entry associated with the memory partition assigned to the at least one core is modified; and an interface module which is configured to provide an interface to the assigning module from user-space.

Claims

1. A system for memory synchronization of a multi-core system, the system comprising:

a processor configured to execute instructions stored in memory to;

operate as an assigning module to assign at least one memory partition to at least one core of the multi-core system;

operate as a mapping module to provide information for a translation lookaside buffer (TLB) shootdown for the multi-core system by sending an interrupt to the at least one core of the multi-core system if a page table entry associated with the memory partition assigned to the at least one core is modified; and

operate as an interface module to provide an interface for the assigning module operations from user-space.

2. The system according to claim 1, wherein when the processor is operating as the mapping module, the processor provides the information for translating the TLB shootdown during a copy-on-write page sharing of the at least one memory partition.

3. The system according to one of claim 1, wherein when the processor is operating as the interface module, the processor provides the interface to the assigning module for the user-space by a set of system calls for controlling a binding of the at least one memory partition to the at least one core.

4. The system according to claim 3, wherein when the processor is operating as the interface module, the processor uses the set of system calls to receive and adapt the TLB shootdown information.

5. A database, comprising

a multi-core system;

a memory system with at least one memory partition; and

a system for memory synchronization of the multi-core system, the system comprising a processor configured to execute instructions stored in memory to;

operate as an assigning module configured to assign at least one memory partition to at least one core of the multi-core system;

operate as a mapping module configured to provide information for translating a TLB shootdown for the multi-core system by sending an interrupt to the at least one core of the multi-core system, if a page table entry associated with the memory partition assigned to the at least one core is modified; and

operate as an interface module which is configured to provide an interface to the assigning module from user-space.

6. The database according to claim 5, wherein the database is a hybrid online transactional processing and online analytical processing database.

7. The database according to claim 6, wherein the database is configured to perform online transaction processing by ensuring that at least one online transactional processing thread operates on one or more of the at least one memory partition.

8. The database according to one of claim 5, wherein the database is enabled to provide a controlled dispatching of the TLB shootdown by using a data structure indicating which of the at least one core is bound to which of the at least one memory partition.

9. The database according to claim 5, wherein the interface module is configured to communicate a binding of the at least one memory partition to the at least one core.

10. The database according to claim 9, wherein the interface module is configured to adapt the TLB shootdown by information as received by using the set of system calls.

11. A method for memory synchronization of a multi-core system performed by a processor executing computer instructions stored in memory, the method comprising:

operating as an assigning module and assigning (S1) at least one memory partition to at least one core of the multi-core system;

providing (S2) a translation lookaside buffer (TLB) shootdown for the multi-core system using a mapping module by sending (S3) an interrupt to the at least one core of the multi-core system, if a page table entry associated with the memory partition assigned to the at least one core is modified; and

providing (S4) an interface to the assigning module to a user-space.

12. The method according to claim 11, wherein the step of providing (S2) the TLB shootdown is performed during a copy-on-write page sharing of the at least one memory partition.

13. The method according to claim 11, wherein the step of providing (S2) TLB shootdown is performed by a set of system calls for controlling a binding of the at least one memory partition to the at least one core.

14. The method according to claim 13, wherein the TLB shootdown is adapted by information as received by using the set of system calls.

15. The method of claim 12 wherein program instructions that define the operations to be performed by the processor are stored in a non-transitory computer readable media.