Flash Memory Cell And Associated Decoders

• US 20170337978A1
• Filed: 05/18/2016
• Published: 11/23/2017
• Est. Priority Date: 05/18/2016
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Tran, Hieu Van, Ly, Anh, Vu, Thuan
• Granted Patent: US 9,953,719 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate

Abstract

The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

Claims

1. A non-volatile memory device comprising:

an array of flash memory cells organized in rows and columns, each flash memory cell comprising a bit line terminal, a word line terminal, an erase gate terminal, a source line terminal, and no other terminals;

a row decoder for receiving row address signals and selecting a row in the array of flash memory cells for a read, program, or erase operation based on the row address signals;

an erase gate decoder for receiving erase gate select signals, selecting one of a plurality of different voltages to generate an erase gate voltage, and applying the erase gate voltage to an erase gate line connected to erase gate terminals of a plurality of flash memory cells in the array;

a source line decoder for receiving source line select signals, selecting one of the plurality of different voltages to generate a source line voltage, and applying the source line voltage to a source line connected to source line terminals of a plurality of flash memory cells in the array; and

a voltage shifter for generating one of the plurality of different voltages.

2. The memory device of claim 1, wherein the row decoder comprises a row decoder circuit for each sector in the array, each sector comprising two row of flash memory cells in the array.

3. The memory device of claim 1, wherein the erase gate decoder comprises a current limiter for limiting the current generated by the application of the erase gate voltage to the erase gate line.

4. The memory device of claim 1, wherein the erase gate decoder comprises a deselect circuit for pulling the output of the erase gate decoder to a low voltage in response to the erase gate select signals.

5. The memory device of claim 1, wherein the erase gate decoder comprises PMOS transistors and no NMOS transistors.

6. The memory device of claim 1, wherein the source line decoder comprises a monitor circuit for providing a monitor line containing the output of the source line decoder.

7. The memory device of claim 1, wherein the source line decoder comprises a read deselect circuit for pulling the output of the source line decoder to a low voltage during a read operation.

8. The memory device of claim 1, wherein the source line decoder comprises a programming deselect circuit for pulling the output of the source line decoder to a low voltage during a programming operation.

9. The memory device of claim 1, wherein the source line decoder comprises NMOS transistors and no PMOS transistors.

10. The memory device of claim 1, wherein the source line decoder comprises PMOS transistors and no NMOS transistors.

11. The memory device of claim 1, wherein the voltage shifter comprises a latch.

12. The memory device of claim 1, wherein the voltage shifter is coupled to a plurality of sectors in the array, each sector comprising two rows of flash memory cells in the array.

13. The memory device of claim 12, wherein the voltage shifter comprises a current limiter used during erase or programming operations for a selected sector among the plurality of sectors.

14. The memory device of claim 12, wherein the voltage shifter comprises a current limiter used during read operations for the selected sector among the plurality of sectors or when no operation is being performed.

15. The memory device of claim 1, wherein the voltage shifter comprises NMOS transistors and no PMOS transistors.

16. The memory device of claim 1, wherein the voltage shifter comprises PMOS transistors and no NMOS transistors.

17. A non-volatile memory device comprising:

an array of flash memory cells organized in rows and columns, each flash memory cell comprising a bit line terminal, a word line terminal, an erase gate terminal, a source line terminal, and no other terminals;

a row decoder for receiving row address signals and selecting a row in the array of flash memory cells for a read, program, or erase operation based on the row address signals;

an erase gate decoder for receiving erase gate select signals, selecting one of a plurality of different voltages to generate an erase gate voltage, and applying the erase gate voltage to an erase gate line connected to erase gate terminals of a plurality of flash memory cells in the array;

a source line decoder for receiving source line select signals, selecting one of the plurality of different voltages to generate a source line voltage, and applying the source line voltage to a source line connected to source line terminals of a plurality of flash memory cells in the array;

a voltage shifter for generating one of the plurality of different voltages; and

a column of dummy flash memory cells, wherein each dummy flash memory cell is not used to store data and one or more of the dummy flash memory cells are coupled to a source line during a read or erase operation to pull the source line down to a low voltage or ground, wherein each source line is coupled to the source line terminals of two rows of flash memory cells in the array.

18. The memory device of claim 17, wherein the row decoder comprises a row decoder circuit for each sector in the array, each sector comprising two row of flash memory cells in the array.

19. The memory device of claim 17, wherein the erase gate decoder comprises a current limiter for limiting the current generated by the application of the erase gate voltage to the erase gate line.

20. The memory device of claim 17, wherein the erase gate decoder comprises a deselect circuit for pulling the output of the erase gate decoder to a low voltage in response to the erase gate select signals.

21. The memory device of claim 17, wherein the erase gate decoder comprises PMOS transistors and no NMOS transistors.

22. The memory device of claim 17, wherein the source line decoder comprises a monitor circuit for providing a monitor line containing the output of the source line decoder.

23. The memory device of claim 17, wherein the source line decoder comprises a read deselect circuit for pulling the output of the source line decoder to a low voltage during a read operation.

24. The memory device of claim 17, wherein the source line decoder comprises a programming deselect circuit for pulling the output of the source line decoder to a low voltage during a programming operation.

25. The memory device of claim 17, wherein the source line decoder comprises NMOS transistors and no PMOS transistors.

26. The memory device of claim 17, wherein the source line decoder comprises PMOS transistors and no NMOS transistors.

27. The memory device of claim 17, wherein the voltage shifter comprises a latch.

28. The memory device of claim 17, wherein the voltage shifter is coupled to a plurality of sectors in the array, each sector comprising two rows of flash memory cells in the array.

29. The memory device of claim 28, wherein the voltage shifter comprises a current limiter used during erase or programming operations for a selected sector among the plurality of sectors.

30. The memory device of claim 28, wherein the voltage shifter comprises a current limiter used during read operations for the selected sector among the plurality of sectors or when no operation is being performed.

31. The memory device of claim 17, wherein the voltage shifter comprises NMOS transistors and no PMOS transistors.

32. The memory device of claim 17, wherein the voltage shifter comprises PMOS transistors and no NMOS transistors.

33. A non-volatile memory device comprising:

an array of flash memory cells organized in rows and columns, each flash memory cell comprising a bit line terminal, a word line terminal, an erase gate terminal, and a source line terminal; and

a high voltage row decoder for receiving select signals, selecting one of the plurality of different voltages to generate application voltages, and applying the application voltages to terminals of a plurality of flash memory cells in the array;

wherein the high voltage row decoder comprises transistors only of a PMOS type.

34. The non-volatile memory device of claim 33, further comprising:

an adaptive high voltage latch level shifter.

35. The non-volatile memory device of claim 33, further comprising:

an erase gate decoder comprising transistors only of the PMOS type.

36. The non-volatile memory device of claim 35, wherein the erase gate decoder comprises only a single PMOS transistor.

37. The non-volatile memory device of claim 33, further comprising:

a current limiter.

38. The non-volatile memory device of claim 33, further comprising:

a source line decoder comprising transistors only of the PMOS type.

39. The non-volatile memory device of claim 33, further comprising:

a control gate decoder comprising transistors only of the PMOS type.

40. The non-volatile memory device of claim 33, wherein the flash memory cells are source side injection tip erase memory cells.

41. A non-volatile memory device comprising:

an array of flash memory cells organized in rows and columns, each flash memory cell comprising a bit line terminal, a word line terminal, an erase gate terminal, a source line terminal, and no other terminals;

a high voltage row decoder for receiving select signals, selecting one of the plurality of different voltages to generate application voltages, and applying the application voltages to terminals of a plurality of flash memory cells in the array; and

a plurality of dummy memory cells within the array arranged to pull down one or more source lines during a read operation.

42. The memory device of claim 41, wherein the row decoder comprises a row decoder circuit for each sector in the array, each sector comprising two row of flash memory cells in the array.

43. The memory device of claim 41, wherein the erase gate decoder comprises a current limiter for limiting the current generated by the application of the erase gate voltage to the erase gate line.

44. The memory device of claim 41, wherein the erase gate decoder comprises a deselect circuit for pulling the output of the erase gate decoder to a low voltage in response to the erase gate select signals.

45. The memory device of claim 41, wherein the erase gate decoder comprises PMOS transistors and no NMOS transistors.

46. The memory device of claim 41, wherein the source line decoder comprises a monitor circuit for providing a monitor line containing the output of the source line decoder.

47. The memory device of claim 41, wherein the source line decoder comprises a read deselect circuit for pulling the output of the source line decoder to a low voltage during a read operation.

48. The memory device of claim 41, wherein the source line decoder comprises a programming deselect circuit for pulling the output of the source line decoder to a low voltage during a programming operation.

49. The memory device of claim 41, wherein the source line decoder comprises NMOS transistors and no PMOS transistors.

50. The memory device of claim 41, wherein the source line decoder comprises PMOS transistors and no NMOS transistors.

51. The memory device of claim 41, wherein the voltage shifter comprises a latch.

52. The memory device of claim 41, wherein the voltage shifter is coupled to a plurality of sectors in the array, each sector comprising two rows of flash memory cells in the array.

53. The memory device of claim 52, wherein the voltage shifter comprises a current limiter used during erase or programming operations for a selected sector among the plurality of sectors.

54. The memory device of claim 52, wherein the voltage shifter comprises a current limiter used during read operations for the selected sector among the plurality of sectors or when no operation is being performed.

55. The memory device of claim 41, wherein the voltage shifter comprises NMOS transistors and no PMOS transistors.

56. The memory device of claim 41, wherein the voltage shifter comprises PMOS transistors and no NMOS transistors.

57. The non-volatile memory device of claim 41, further comprising:

an adaptive high voltage latch level shifter.

58. The non-volatile memory device of claim 41, further comprising:

an erase gate decoder comprising transistors only of the PMOS type.

59. The non-volatile memory device of claim 58, wherein the erase gate decoder comprises only a single PMOS transistor.

60. The non-volatile memory device of claim 41, further comprising:

a current limiter.

61. The non-volatile memory device of claim 41, further comprising:

a source line decoder comprising transistors only of the PMOS type.

62. The non-volatile memory device of claim 41, further comprising:

a control gate decoder comprising transistors only of the PMOS type.

63. The non-volatile memory device of claim 41, wherein the flash memory cells are source side injection tip erase memory cells.